Part Number Hot Search : 
DG202ADY 4LCX1 27C16 WT11T SL4049BN 2SK1726 A0000 GROUP
Product Description
Full Text Search
 

To Download EM65567AGH Datasheet File
  If you can't view the Datasheet, Please click here to try to view without PDF Reader .  
　
 

  Datasheet File OCR Text:
 Elan Microelectronics Crop.
lim re P
EM65567
ry a in
66COM/ 96SEG 256 Color STN LCD Driver
January 9, 2003 Version 0.1 ( Preliminary )
Version 0.1
EM65567 Specification Revision History Content Initial version
Date January 9, 2003
lim re P
ry a in
Caution: The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Contents
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. GENERAL DESCRIPTION ..............................................................................................................................................4 FEATURE ...........................................................................................................................................................................4 APPLICATIONS ................................................................................................................................................................4 PIN CONFIGURATIONS..................................................................................................................................................5 FUNCTIONAL BLOCK DIAGRAM .............................................................................................................................13 PIN DESCRIPTION.........................................................................................................................................................15 FUNCTIONAL DESCRIPTION.....................................................................................................................................19 CONTROL REGISTER...................................................................................................................................................48 RELATIONSHIP BETWEEN SETTING AND COMMON/DISPLAY RAM............................................................74 ABSOLUTE MAXIMUM RATINGS.........................................................................................................................75 DC CHARACTERISTICS ..........................................................................................................................................76 AC CHARACTERISTIC ............................................................................................................................................79 APPLICATION CIRCUIT..........................................................................................................................................87 COF INFORMATION.................................................................................................................................................91
lim re P
ry a in
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
1. General description
EM65567 is one of the industry's most advanced wide-screen STN-LCD drivers for 256-color display. The industry's first sub-screen display function makes it possible to display different images and data in a sub-screen inside the main LCD screen. It also has a built-in display RAM, a power supply circuit for LCD drive, and an LCD controller circuit, therefore contributing to compact system design. Its partial display function realizes low power consumption. *Partial display function: A function that utilizes only part of the screen, thus reducing power consumption.
2. Feature
Display RAM capacity Graphic: 96*64*(3+3+2)=49,152 bits Icons: 96*2*(3+3+2)=1,536 bits Ratio of display duty cycle: 1/10, 1/18, 1/26, 1/34, 1/42, 1/50, 1/58, 1/66 Outputs Segment:96 RGB (288) outputs, Common: 66 outputs Static driver: 2 outputs Built-in display RAM and power supply circuit Partial display functions Switchable display in black and white mode Serial interface is available
Bus connection with 80-family/ 68-family /Elan MCU Logic power supply voltage: 1.8 to 3.3 V LCD driving voltage: 5.0 to 12.0 V Booster: 2 to 4 times Write system cycle: 140 ns Part Number EM65567AGH EM65567AF
lim re P
Package Gold bumped chip COF EM65567AF
ry a in
Package information Page 5 Page 91
Package (Ordering information): Description NA 64x96RGB (Version A)
Note: The EM65567 series has the following sub-codes depending on their shapes. H: Bare chip (Aluminum pad without bumped); GH: Gold bumped chip; F: COF package; T: TAB (TCP) package Example EM65567: Elan number ; A: Package Version ; F: COF package
3. Applications
Mobile phone DSC Small PDA
* This specification is subject to be changed without notice.
4
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
4.
Pin configurations
521 522 228 227
U -Left
U -R ight
EM65567
D -Left D -R ight
551
Note: With the Elan logo in upper left the pin 1 is in the down left corner.
Mark
U-Left D-Left
lim re P
Coordinate (X,Y) -7241.1 ,141.6 -7241.1 ,-208.4
1
Figure 1. Pin configuration
ry a in
197
Coordinate (X,Y) 7247.9,141.6 7247.9,-208.4
198
Mark
U-Right D-Right
* This specification is subject to be changed without notice.
5
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
PIN DIMENSIONS
Item Chip size
Pad No. 1,197 2 ~ 196 198,227,228 521,522,551 199 ~ 226 229~ 520 523 ~ 550 1, 197 2 ~ 196 198, 227, 522, 551 228, 521 199~226 229 ~ 520 523 ~ 550
Size X 15450 82 70 56 50 70 46 63 48 63 36 63 Y 1770
Unit
Pad Pitch
Bump Size
Die thickness
(excluding bumps)
Bump Height Minimum Bump Gap Coordinate Origin
lim re P
526 +/- 25
ry a in
63 63 48 63 36 63 36
m
All Pad 17 +/- 3 (within die) 14 Chip center
* This specification is subject to be changed without notice.
6
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
PAD Coordinates Table Coordinate (X,Y) -7299.9 ,-765.0 -7217.9 ,-765.0 -7147.9 ,-765.0 -7077.9 ,-765.0 -7007.9 ,-765.0 -6937.9 ,-765.0 -6867.9 ,-765.0 -6797.9 ,-765.0 -6727.9 ,-765.0 -6657.9 ,-765.0 -6587.9 ,-765.0 -6517.9 ,-765.0 -6447.9 ,-765.0 -6377.9 ,-765.0 -6307.9 ,-765.0 -6237.9 ,-765.0 -6167.9 ,-765.0 -6097.9 ,-765.0 -6027.9 ,-765.0 -5957.9 ,-765.0 -5887.9 ,-765.0 -5817.9 ,-765.0 -5747.9 ,-765.0 -5677.9 ,-765.0 -5607.9 ,-765.0 -5537.9 ,-765.0 -5467.9 ,-765.0 -5397.9 ,-765.0 -5327.9 ,-765.0 -5257.9 ,-765.0 -5187.9 ,-765.0 -5117.9 ,-765.0 -5047.9 ,-765.0 -4977.9 ,-765.0 -4907.9 ,-765.0 -4837.9 ,-765.0 -4767.9 ,-765.0 -4485.6 ,-765.0 -4415.6 ,-765.0 -4345.6 ,-765.0 -4275.6 ,-765.0 -4205.6 ,-765.0 -4135.6 ,-765.0 -4065.6 ,-765.0 -3995.6 ,-765.0 -3925.6 ,-765.0 -3855.6 ,-765.0 -3785.6 ,-765.0 -3715.6 ,-765.0 -3645.6 ,-765.0 Coordinate (X,Y) -3575.6 ,-765.0 -3505.6 ,-765.0 -3435.6 ,-765.0 -3365.6 ,-765.0 -3295.6 ,-765.0 -3225.6 ,-765.0 -3155.6 ,-765.0 -3085.6 ,-765.0 -3015.6 ,-765.0 -2945.6 ,-765.0 -2875.6 ,-765.0 -2805.6 ,-765.0 -2735.6 ,-765.0 -2665.6 ,-765.0 -2595.6 ,-765.0 -2525.6 ,-765.0 -2455.6 ,-765.0 -2385.6 ,-765.0 -2315.6 ,-765.0 -2245.6 ,-765.0 -2175.6 ,-765.0 -2105.6 ,-765.0 -2035.6 ,-765.0 -1965.6 ,-765.0 -1895.6 ,-765.0 -1825.6 ,-765.0 -1755.6 ,-765.0 -1473.3 ,-765.0 -1403.3 ,-765.0 -1333.3 ,-765.0 -1263.3 ,-765.0 -1193.3 ,-765.0 -1123.3 ,-765.0 -1053.3 ,-765.0 -983.3 ,-765.0 -913.3 ,-765.0 -843.3 ,-765.0 -773.3 ,-765.0 -703.3 ,-765.0 -633.3 ,-765.0 -563.3 ,-765.0 -493.3 ,-765.0 -423.3 ,-765.0 -353.3 ,-765.0 -283.3 ,-765.0 -213.3 ,-765.0 -143.3 ,-765.0 -73.3 ,-765.0 -3.3 ,-765.0 66.7 ,-765.0
Pin NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Pad Name DUMMY DUMMY DUMMY DUMMY DUMMY SSEG V0 V0 V0 V0 V0 V1 V1 V1 V1 V1 V2 V2 V2 V2 V2 V3 V3 V3 V3 V3 V4 V4 V4 V4 V4 VSSH VSSH VSSH VSSH VSSH DUMMY DUMMY DUMMY DUMMY DUMMY VSSL VSSL VSSL VSSL VSSL TEST TEST RESB RESB
Pin NO 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Pad Name CSB CSB RS RS VSS VSS VSS VSS M/S M/S VDD VDD VDD VDD P/S P/S M86 M86 VSS VSS VSS VSS VSS WRB WRB RDB RDB VDD VDD VDD VDD VDD D0 D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 D8 D8
lim re P
ry a in
* This specification is subject to be changed without notice.
7
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
Pin NO 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Pad Name D9 D9 D10 D10 D11 D11 D12 D12 D13 D13 D14 D14 D15 D15 LP LP FLM FLM M M CLK CLK VSS VSS VSS VSS VSS CK CK CKS CKS VDD VDD VDD VDD VDD DUMMY DUMMY DUMMY DUMMY DUMMY VREF VREF VREF VREF VREF VEE VEE VEE VEE
lim re P
Coordinate (X,Y) 136.7 ,-765.0 206.7 ,-765.0 276.7 ,-765.0 346.7 ,-765.0 416.7 ,-765.0 486.7 ,-765.0 556.7 ,-765.0 626.7 ,-765.0 696.7 ,-765.0 766.7 ,-765.0 836.7 ,-765.0 906.7 ,-765.0 976.7 ,-765.0 1046.7 ,-765.0 1116.7 ,-765.0 1186.7 ,-765.0 1469.0 ,-765.0 1539.0 ,-765.0 1609.0 ,-765.0 1679.0 ,-765.0 1749.0 ,-765.0 1819.0 ,-765.0 1889.0 ,-765.0 1959.0 ,-765.0 2029.0 ,-765.0 2099.0 ,-765.0 2169.0 ,-765.0 2239.0 ,-765.0 2309.0 ,-765.0 2379.0 ,-765.0 2449.0 ,-765.0 2519.0 ,-765.0 2589.0 ,-765.0 2659.0 ,-765.0 2729.0 ,-765.0 2799.0 ,-765.0 2869.0 ,-765.0 2939.0 ,-765.0 3009.0 ,-765.0 3079.0 ,-765.0 3149.0 ,-765.0 3219.0 ,-765.0 3289.0 ,-765.0 3359.0 ,-765.0 3429.0 ,-765.0 3499.0 ,-765.0 3569.0 ,-765.0 3639.0 ,-765.0 3709.0 ,-765.0 3779.0 ,-765.0
Pin NO 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Pad Name VEE VREG VREG VREG VREG VREG VOUT VOUT VOUT VOUT VOUT CAP1CAP1CAP1CAP1CAP1CAP1+ CAP1+ CAP1+ CAP1+ CAP1+ CAP2CAP2CAP2CAP2CAP2CAP2+ CAP2+ CAP2+ CAP2+ CAP2+ CAP3CAP3CAP3CAP3CAP3CAP3+ CAP3+ CAP3+ CAP3+ CAP3+ SCOM DUMMY DUMMY DUMMY DUMMY DUMMY COM31 COM30 COM29
ry a in
Coordinate (X,Y) 3849.0 ,-765.0 3919.0 ,-765.0 3989.0 ,-765.0 4059.0 ,-765.0 4129.0 ,-765.0 4199.0 ,-765.0 4481.3 ,-765.0 4551.3 ,-765.0 4621.3 ,-765.0 4691.3 ,-765.0 4761.3 ,-765.0 4831.3 ,-765.0 4901.3 ,-765.0 4971.3 ,-765.0 5041.3 ,-765.0 5111.3 ,-765.0 5181.3 ,-765.0 5251.3 ,-765.0 5321.3 ,-765.0 5391.3 ,-765.0 5461.3 ,-765.0 5531.3 ,-765.0 5601.3 ,-765.0 5671.3 ,-765.0 5741.3 ,-765.0 5811.3 ,-765.0 5881.3 ,-765.0 5951.3 ,-765.0 6021.3 ,-765.0 6091.3 ,-765.0 6161.3 ,-765.0 6231.3 ,-765.0 6301.3 ,-765.0 6371.3 ,-765.0 6441.3 ,-765.0 6511.3 ,-765.0 6581.3 ,-765.0 6651.3 ,-765.0 6721.3 ,-765.0 6791.3 ,-765.0 6861.3 ,-765.0 6931.3 ,-765.0 7001.3 ,-765.0 7071.3 ,-765.0 7141.3 ,-765.0 7211.3 ,-765.0 7293.3 ,-765.0 7605.0 ,-726.0 7605.0 ,-670.0 7605.0 ,-620.0
* This specification is subject to be changed without notice.
8
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
Pin NO 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250
Pad Name COM28 COM27 COM26 COM25 COM24 COM23 COM22 COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 COM0 COMA SEGA0 SEGB0 SEGC0 SEGA1 SEGB1 SEGC1 SEGA2 SEGB2 SEGC2 SEGA3 SEGB3 SEGC3 SEGA4 SEGB4 SEGC4 SEGA5 SEGB5 SEGC5 SEGA6 SEGB6
lim re P
Coordinate (X,Y) 7605.0 ,-570. 7605.0 ,-520. 7605.0 ,-470. 7605.0 ,-420. 7605.0 ,-370. 7605.0 ,-320. 7605.0 ,-270. 7605.0 ,-220. 7605.0 ,-170. 7605.0 ,-120. 7605.0 ,-70.0 7605.0 ,-20.0 7605.0 ,30.0 7605.0 ,80.0 7605.0 ,130.0 7605.0 ,180.0 7605.0 ,230.0 7605.0 ,280.0 7605.0 ,330.0 7605.0 ,380.0 7605.0 ,430.0 7605.0 ,480.0 7605.0 ,530.0 7605.0 ,580.0 7605.0 ,630.0 7605.0 ,680.0 7605.0 ,736.0 7331.0 ,765.0 7275.0 ,765.0 7225.0 ,765.0 7175.0 ,765.0 7125.0 ,765.0 7075.0 ,765.0 7025.0 ,765.0 6975.0 ,765.0 6925.0 ,765.0 6875.0 ,765.0 6825.0 ,765.0 6775.0 ,765.0 6725.0 ,765.0 6675.0 ,765.0 6625.0 ,765.0 6575.0 ,765.0 6525.0 ,765.0 6475.0 ,765.0 6425.0 ,765.0 6375.0 ,765.0 6325.0 ,765.0 6275.0 ,765.0 6225.0 ,765.0
Pin NO 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300
Pad Name SEGC6 SEGA7 SEGB7 SEGC7 SEGA8 SEGB8 SEGC8 SEGA9 SEGB9 SEGC9 SEGA10 SEGB10 SEGC10 SEGA11 SEGB11 SEGC11 SEGA12 SEGB12 SEGC12 SEGA13 SEGB13 SEGC13 SEGA14 SEGB14 SEGC14 SEGA15 SEGB15 SEGC15 SEGA16 SEGB16 SEGC16 SEGA17 SEGB17 SEGC17 SEGA18 SEGB18 SEGC18 SEGA19 SEGB19 SEGC19 SEGA20 SEGB20 SEGC20 SEGA21 SEGB21 SEGC21 SEGA22 SEGB22 SEGC22 SEGA23
ry a in
Coordinate (X,Y) 6175.0 ,765.0 6125.0 ,765.0 6075.0 ,765.0 6025.0 ,765.0 5975.0 ,765.0 5925.0 ,765.0 5875.0 ,765.0 5825.0 ,765.0 5775.0 ,765.0 5725.0 ,765.0 5675.0 ,765.0 5625.0 ,765.0 5575.0 ,765.0 5525.0 ,765.0 5475.0 ,765.0 5425.0 ,765.0 5375.0 ,765.0 5325.0 ,765.0 5275.0 ,765.0 5225.0 ,765.0 5175.0 ,765.0 5125.0 ,765.0 5075.0 ,765.0 5025.0 ,765.0 4975.0 ,765.0 4925.0 ,765.0 4875.0 ,765.0 4825.0 ,765.0 4775.0 ,765.0 4725.0 ,765.0 4675.0 ,765.0 4625.0 ,765.0 4575.0 ,765.0 4525.0 ,765.0 4475.0 ,765.0 4425.0 ,765.0 4375.0 ,765.0 4325.0 ,765.0 4275.0 ,765.0 4225.0 ,765.0 4175.0 ,765.0 4125.0 ,765.0 4075.0 ,765.0 4025.0 ,765.0 3975.0 ,765.0 3925.0 ,765.0 3875.0 ,765.0 3825.0 ,765.0 3775.0 ,765.0 3725.0 ,765.0
* This specification is subject to be changed without notice.
9
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
Pin NO 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350
Pad Name SEGB23 SEGC23 SEGA24 SEGB24 SEGC24 SEGA25 SEGB25 SEGC25 SEGA26 SEGB26 SEGC26 SEGA27 SEGB27 SEGC27 SEGA28 SEGB28 SEGC28 SEGA29 SEGB29 SEGC29 SEGA30 SEGB30 SEGC30 SEGA31 SEGB31 SEGC31 SEGA32 SEGB32 SEGC32 SEGA33 SEGB33 SEGC33 SEGA34 SEGB34 SEGC34 SEGA35 SEGB35 SEGC35 SEGA36 SEGB36 SEGC36 SEGA37 SEGB37 SEGC37 SEGA38 SEGB38 SEGC38 SEGA39 SEGB39 SEGC39
lim re P
Coordinate (X,Y) 3675.0 ,765.0 3625.0 ,765.0 3575.0 ,765.0 3525.0 ,765.0 3475.0 ,765.0 3425.0 ,765.0 3375.0 ,765.0 3325.0 ,765.0 3275.0 ,765.0 3225.0 ,765.0 3175.0 ,765.0 3125.0 ,765.0 3075.0 ,765.0 3025.0 ,765.0 2975.0 ,765.0 2925.0 ,765.0 2875.0 ,765.0 2825.0 ,765.0 2775.0 ,765.0 2725.0 ,765.0 2675.0 ,765.0 2625.0 ,765.0 2575.0 ,765.0 2525.0 ,765.0 2475.0 ,765.0 2425.0 ,765.0 2375.0 ,765.0 2325.0 ,765.0 2275.0 ,765.0 2225.0 ,765.0 2175.0 ,765.0 2125.0 ,765.0 2075.0 ,765.0 2025.0 ,765.0 1975.0 ,765.0 1925.0 ,765.0 1875.0 ,765.0 1825.0 ,765.0 1775.0 ,765.0 1725.0 ,765.0 1675.0 ,765.0 1625.0 ,765.0 1575.0 ,765.0 1525.0 ,765.0 1475.0 ,765.0 1425.0 ,765.0 1375.0 ,765.0 1325.0 ,765.0 1275.0 ,765.0 1225.0 ,765.0
Pin NO 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400
Pad Name SEGA40 SEGB40 SEGC40 SEGA41 SEGB41 SEGC41 SEGA42 SEGB42 SEGC42 SEGA43 SEGB43 SEGC43 SEGA44 SEGB44 SEGC44 SEGA45 SEGB45 SEGC45 SEGA46 SEGB46 SEGC46 SEGA47 SEGB47 SEGC47 SEGA48 SEGB48 SEGC48 SEGA49 SEGB49 SEGC49 SEGA50 SEGB50 SEGC50 SEGA51 SEGB51 SEGC51 SEGA52 SEGB52 SEGC52 SEGA53 SEGB53 SEGC53 SEGA54 SEGB54 SEGC54 SEGA55 SEGB55 SEGC55 SEGA56 SEGB56
ry a in
Coordinate (X,Y) 1175.0 ,765.0 1125.0 ,765.0 1075.0 ,765.0 1025.0 ,765.0 975.0 ,765.0 925.0 ,765.0 875.0 ,765.0 825.0 ,765.0 775.0 ,765.0 725.0 ,765.0 675.0 ,765.0 625.0 ,765.0 575.0 ,765.0 525.0 ,765.0 475.0 ,765.0 425.0 ,765.0 375.0 ,765.0 325.0 ,765.0 275.0 ,765.0 225.0 ,765.0 175.0 ,765.0 125.0 ,765.0 75.0 ,765.0 25.0 ,765.0 -25.0 ,765.0 -75.0 ,765.0 -125.0 ,765.0 -175.0 ,765.0 -225.0 ,765.0 -275.0 ,765.0 -325.0 ,765.0 -375.0 ,765.0 -425.0 ,765.0 -475.0 ,765.0 -525.0 ,765.0 -575.0 ,765.0 -625.0 ,765.0 -675.0 ,765.0 -725.0 ,765.0 -775.0 ,765.0 -825.0 ,765.0 -875.0 ,765.0 -925.0 ,765.0 -975.0 ,765.0 -1025.0 ,765.0 -1075.0 ,765.0 -1125.0 ,765.0 -1175.0 ,765.0 -1225.0 ,765.0 -1275.0 ,765.0
* This specification is subject to be changed without notice.
10
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
Pin NO 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450
Pad Name SEGC56 SEGA57 SEGB57 SEGC57 SEGA58 SEGB58 SEGC58 SEGA59 SEGB59 SEGB59 SEGA60 SEGB60 SEGC60 SEGA61 SEGB61 SEGC61 SEGA62 SEGB62 SEGC62 SEGA63 SEGB63 SEGC63 SEGA64 SEGB64 SEGC64 SEGA65 SEGB65 SEGC65 SEGA66 SEGB66 SEGC66 SEGA67 SEGB67 SEGC67 SEGA68 SEGB68 SEGC68 SEGA69 SEGB69 SEGC69 SEGA70 SEGB70 SEGC70 SEGA71 SEGB71 SEGC71 SEGA72 SEGB72 SEGC72 SEGA73
lim re P
Coordinate (X,Y) -1325.0 ,765.0 -1375.0 ,765.0 -1425.0 ,765.0 -1475.0 ,765.0 -1525.0 ,765.0 -1575.0 ,765.0 -1625.0 ,765.0 -1675.0 ,765.0 -1725.0 ,765.0 -1775.0 ,765.0 -1825.0 ,765.0 -1875.0 ,765.0 -1925.0 ,765.0 -1975.0 ,765.0 -2025.0 ,765.0 -2075.0 ,765.0 -2125.0 ,765.0 -2175.0 ,765.0 -2225.0 ,765.0 -2275.0 ,765.0 -2325.0 ,765.0 -2375.0 ,765.0 -2425.0 ,765.0 -2475.0 ,765.0 -2525.0 ,765.0 -2575.0 ,765.0 -2625.0 ,765.0 -2675.0 ,765.0 -2725.0 ,765.0 -2775.0 ,765.0 -2825.0 ,765.0 -2875.0 ,765.0 -2925.0 ,765.0 -2975.0 ,765.0 -3025.0 ,765.0 -3075.0 ,765.0 -3125.0 ,765.0 -3175.0 ,765.0 -3225.0 ,765.0 -3275.0 ,765.0 -3325.0 ,765.0 -3375.0 ,765.0 -3425.0 ,765.0 -3475.0 ,765.0 -3525.0 ,765.0 -3575.0 ,765.0 -3625.0 ,765.0 -3675.0 ,765.0 -3725.0 ,765.0 -3775.0 ,765.0
Pin NO 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500
Pad Name SEGB73 SEGC73 SEGA74 SEGB74 SEGC74 SEGA75 SEGB75 SEGC75 SEGA76 SEGB76 SEGC76 SEGA77 SEGB77 SEGC77 SEGA78 SEGB78 SEGC78 SEGA79 SEGB79 SEGC79 SEGA80 SEGB80 SEGC80 SEGA81 SEGB81 SEGC81 SEGA82 SEGB82 SEGC82 SEGA83 SEGB83 SEGC83 SEGA84 SEGB84 SEGC84 SEGA85 SEGB85 SEGC85 SEGA86 SEGB86 SEGC86 SEGA87 SEGB87 SEGC87 SEGA88 SEGB88 SEGC88 SEGA89 SEGB89 SEGC89
ry a in
Coordinate (X,Y) -3825.0 ,765.0 -3875.0 ,765.0 -3925.0 ,765.0 -3975.0 ,765.0 -4025.0 ,765.0 -4075.0 ,765.0 -4125.0 ,765.0 -4175.0 ,765.0 -4225.0 ,765.0 -4275.0 ,765.0 -4325.0 ,765.0 -4375.0 ,765.0 -4425.0 ,765.0 -4475.0 ,765.0 -4525.0 ,765.0 -4575.0 ,765.0 -4625.0 ,765.0 -4675.0 ,765.0 -4725.0 ,765.0 -4775.0 ,765.0 -4825.0 ,765.0 -4875.0 ,765.0 -4925.0 ,765.0 -4975.0 ,765.0 -5025.0 ,765.0 -5075.0 ,765.0 -5125.0 ,765.0 -5175.0 ,765.0 -5225.0 ,765.0 -5275.0 ,765.0 -5325.0 ,765.0 -5375.0 ,765.0 -5425.0 ,765.0 -5475.0 ,765.0 -5525.0 ,765.0 -5575.0 ,765.0 -5625.0 ,765.0 -5675.0 ,765.0 -5725.0 ,765.0 -5775.0 ,765.0 -5825.0 ,765.0 -5875.0 ,765.0 -5925.0 ,765.0 -5975.0 ,765.0 -6025.0 ,765.0 -6075.0 ,765.0 -6125.0 ,765.0 -6175.0 ,765.0 -6225.0 ,765.0 -6275.0 ,765.0
* This specification is subject to be changed without notice.
11
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
Pin NO 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550
Pad Name SEGA90 SEGB90 SEGC90 SEGA91 SEGB91 SEGC91 SEGA92 SEGB92 SEGC92 SEGA93 SEGB93 SEGC93 SEGA94 SEGB94 SEGC94 SEGA95 SEGB95 SEGC95 COM32 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 COM63
lim re P
Coordinate (X,Y) -6325.0 ,765.0 -6375.0 ,765.0 -6425.0 ,765.0 -6475.0 ,765.0 -6525.0 ,765.0 -6575.0 ,765.0 -6625.0 ,765.0 -6675.0 ,765.0 -6725.0 ,765.0 -6775.0 ,765.0 -6825.0 ,765.0 -6875.0 ,765.0 -6925.0 ,765.0 -6975.0 ,765.0 -7025.0 ,765.0 -7075.0 ,765.0 -7125.0 ,765.0 -7175.0 ,765.0 -7225.0 ,765.0 -7275.0 ,765.0 -7331.0 ,765.0 -7605.0 ,736.0 -7605.0 ,680.0 -7605.0 ,630.0 -7605.0 ,580.0 -7605.0 ,530.0 -7605.0 ,480.0 -7605.0 ,430.0 -7605.0 ,380.0 -7605.0 ,330.0 -7605.0 ,280.0 -7605.0 ,230.0 -7605.0 ,180.0 -7605.0 ,130.0 -7605.0 ,80.0 -7605.0 ,30.0 -7605.0 ,-20.0 -7605.0 ,-70.0 -7605.0 ,-120.0 -7605.0 ,-170.0 -7605.0 ,-220.0 -7605.0 ,-270.0 -7605.0 ,-320.0 -7605.0 ,-370.0 -7605.0 ,-420.0 -7605.0 ,-470.0 -7605.0 ,-520.0 -7605.0 ,-570.0 -7605.0 ,-620.0 -7605.0 ,-670.0
Pin NO 551
Pad Name COMB
Coordinate (X,Y) -7605.0 ,-726.0
ry a in
* This specification is subject to be changed without notice.
12
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
5.
Functional block diagram
5.1 System Block Diagram
SEGA1 CO M63 CO MB SEGA0 SEGB0 SEGC0 SEGB1 SEGC1 SEGA94 SEGB94 SEGC94 SEGA95 SEGB95 SEGC95 SEGC95 SEGC95 CO MA CO M0
VDD V0 V1 V2 V3 V4 VSS (VSSH,VSSL) CAP1CAP1+ CAP2CAP2+ CAP3CAP3+ VO UT VEE VREF VREG D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1/SDA D0/SCL
---Common Driver
---------Segment Driver G radation Selection Circuit Static Driver
Shift Register Data Latch
Data Latch
Line Address Decoder
Display Line Register
Display Line Counter
Voltage Converter
CSB RS
Y Address Register
Y Address Decoder
Y Address Counter
lim re P
RAM Interface
* This specification is subject to be changed without notice.
Booster Circuit Input/Output Buffer
Display RAM (DDRAM) 96 X 64 X (3+3+2) bits
Pixel Display RAM (PG RAM) 96 X 2 X (3+3+2) bits X Address Decoder
X Address Counter
X Address Register
ry a in
Instruction Decoder Register Read O SC Display T iming G en. CK CKS CLK LP FLM M
Alternation Circuit
Bus Holder
MPU Interface
M/S RDB W RB P/S M86 RESB T EST (E) (R/W B)
Figure 2. System Block Diagram
13
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
5.2 Power Circuit Block Diagram
CAP1CAP2CAP3CAP1+ CAP2+ CAP3+ VO UT Booster Circuit
+ -
V0
VEE
V1 Div iding Resistor V2
VREG AMP VREF
+ -
VREG
+ + -
Bias Register
V3
V4
Electronic Volume Register
Booster step set Register
Figure 3. Power Circuit Block Diagram
lim re P
ry a in
Im pedence Conv erter
* This specification is subject to be changed without notice.
14
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
6.
Pin Description
6.1 Power Supply Pins Symbol VDD VSSL VSSH V0 V1 V2 V3 V4 I/O Power Supply Power Supply Power Supply Power Supply Description Power supply pin for logic circuit to +1.8 to 3.3V Ground pin for logic circuit, connect to 0V Ground pin for high voltage circuit, connected to 0V Bias power supply pin for LCD drive voltage When using an external power supply, convert impedance by using resistance-division of LCD drive power supply or operation amplifier before adding voltage to the pins. These voltages should have following relationship: VSS6.2 LCD Power Supply Circuit Pins Symbol CAP1+ CAP1CAP2+ CAP2 CAP3+ CAP3VREF VEE VOUT VREG I/O O
I Power Supply O O
lim re P
O O O O O
Description Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP1- and CAP1+. Connecting pin for the built in booster's capacitor - side. The capacitor is connected between CAP1- and CAP1+. Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP2- and CAP2+. Connecting pin for the built in booster's capacitor - side. The capacitor is connected between CAP2- and CAP2+. Connecting pin for the built in booster's capacitor + side. The capacitor is connected between CAP3- and CAP3+. Connecting pin for the built in booster's capacitor - side. The capacitor is connected between CAP3- and CAP3+. Voltage input pin for generating reference power source
ry a in
Voltage supply pin for booster circuit. Usually the same voltage level as VDD.
Output pin of boosted voltage in the built-in booster. The capacitor must be connected between this pin and VSS. Output pin for regulated voltage of VREG AMP. The capacitor must be connected between this pin and VSS.
* This specification is subject to be changed without notice.
15
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
6.3 System Bus Pins Symbol RESB I/O I Description Reset input pin. When RESB is "L", initialization is executed. Data bus / Signal interface related pins. When parallel interface is selected (P/S = "H"), The D7-D0 are 8-bits bi-directional data bus, connect to MPU data bus. When serial interface is selected (P/S = "L"), D0 and D1 (SCL, SDA) are used as serial interface pins. SCL: Input pin for data transfer clock SDA: Serial data input pin SDA data is latched at the rising edge of SCL. Internal serial/parallel conversion into 8-bit data occurs at the rising edge of 8th clock of SCL After completing data transferring, or when making no access, be sure to set SCL to "L". 8-bit bi-directional bus. Connected to MPU data bus. Used as data bus for upper 8-pins in the 16-bits data RAM transfer mode. Chip Select input pin. CSB = "L": accepts access from MPU CSB = "H": denies access from MPU RAM/Register select input pin. RS = "0": D7-D0 are display RAM data RS = "1": D7-D0 are control register data Read/Write control pin Select 80-family MPU type (M86 = "L") The RDB is a data read signal. When RDB is "L", D7-D0 are in an output status. Select 68-family MPU type (M86 = "H") R/WB = "H": When E is "H", D7-D0 are in an output status. R/WB = "L": The data on D7-D0 are latched at falling edge of the E signal. Read/Write control pin Select 80-family MPU type (M86 = "L") The WRB is a data write signal. The data on D7-D0 are latched at rising edge of the WRB signal. Select 68-family MPU type (M86 = "H") Read/Write control input pin. R/W = "H": Read R/W = "L": Write MPU interface type selecting input pin. M86 = "H": 68-family interface M86 = "L": 80-family interface Fixed at either "H" or "L" Parallel/Serial interface select pin. P/S Chip select Data identification Data Read/Write Serial clock H CSB RS D0-D7 RDB, WRB L CSB RS SDA Write only SCL P/S = "H": For parallel interface. P/S = "L": For serial interface. Fix D15-D5 pins are Hi-Z, RDB and WRB pins to either "H" or "L". For testing. Fix to "L".
D0/SCL D1/SDA D2-D7
I/O
D8-D15 CSB RS
I/O I I
RDB (E)
WRB (R/WB)
lim re P
I I I I I
ry a in
M86
P/S
TEST
* This specification is subject to be changed without notice.
16
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
6.4 LCD Drive Circuit Signals Symbol LP I/O I/O Description The LP is latch clock I/O pin. At the rising edge, count the display line counter. At the falling edge output the LCD drive signal. This pin use in master/slave multi-chip system M/S = "H": LP is output M/S = "L": LP is input I/O pin for LCD display synchronous signals (first line maker). When FLM pin is set to "H", the display start-line address is preset. This pin use in master/slave multi-chip system. In the display line counter M/S = "H": FLM is output M/S = "L": FLM is input I/O pin for alternated signals of LCD drive output. M/S = "H": M is output M/S = "L": M is input This pin use in master/slave multi-chip system. Maser/Slave mode select input pin M/S State OSC Power Supply Circuit LP FLM M CLK H Master Enable Enable Output Output Output Output L Slave Disable Disable Input Input Input Input Fix to "H" or "L" at this terminal. Segment output pins for LCD drives. According to the data of the Display RAM data, non-lighted at "0", lighted at "1" (Normal Mode). non-lighted at "1", lighted at "0" (Reverse Mode) and, by a combination of M signal and display data, one signal level among V0,V2,V3 and VSS signal levels are selected. (When Monochrome Display)
M Signal
FLM
I/O
M
I/O
M/S
I
SEGA0-A95 SEGB0-B95 SEGC0-C95
lim re P
O
Display RAM Data Normal M ode V2 V0 V3 Reverse M ode V0 V2 VSS
ry a in
VSS V3
COM0COM63
O
COMA COMB SCOM SSEG
O O O
Common output pins for LCD drivers. By a combination of the scanning data and M signal, one signal level among V0, V1, V4 and VSS signal level is selected. Data M Output level H H VSS L H V1 H L V0 L L V4 Common output pin for LCD drive exclusively for icons. Common output pin for LCD drive exclusively for icons. LCD driver output pin for static driver
* This specification is subject to be changed without notice.
17
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
6.5 Oscillating Circuit Pin Symbol CKS CK CLK I/O I I I/O Description Display timing clock source select input pin. CKS = "H": Use external clock from CK pin. CKS = "L": Use internal oscillated clock. In the slave mode, fix this pin at "L". In the case of TCP, draw it as a separate terminal. External clock input pin for display timing. In the slave mode, fix the CK pin at "L". I/O pin for display timing clock. To use this pin in the master/slave system. M/S = "H": Output in the master mode. M/S = "L": Input display timing clock from the master. In the monochrome mode, this signal is not output signal.
lim re P
ry a in
* This specification is subject to be changed without notice.
18
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
7.
Functional Description
7.1 MPU Interface 7.1.1 Selection of Interface Type The EM65567 transfers data through 8-bit parallel I/O (D7-D0), 16-bit parallel I/O (D15-D0) or serial data input (SDA, SCL). The parallel interface or serial interface can select by state of P/S pin. When select serial interface, data reading cannot be performed, only data writing can operate. P/S H L I/F Type Parallel Serial CSB CSB CSB RS RS RS RDB RDB WRB WRB M86 M86 SDA SDA SCL SCL Data D7~D0 (D15~D0) -
7.1.2 Parallel Input When parallel interface is selected with the P/S pin, the EM65567 allows data to be transferred in parallel to an 8-bit/16-bit MPU through the data bus. For the 8-bit/16-bit MPU, either the 80-family MPU interface or the 68-family MPU interface can be selected with the m86 pin. M86 H L MPU Type 68-family MPU 80-family MPU
7.1.3 Read/Write functions of Register and display RAM RS, RDB and WRB signals. RS 1 1 0 0 68-family R/WB 1 0 1 0
The EM65567 have four read/write functions at parallel interface mode. Each read/write function select by combinations of
lim re P
80-family RDB WRB 0 1 1 0 0 1 1 0
CSB CSB CSB
RS RS RS
RDB E RDB
WRB R/WB WRB
Data D7~D0 (D15~D0) D0~D7 (D15~D0)
ry a in
Function
Read internal Register Write internal Register Read display data Write display data
7.1.4 Serial Interface The serial interface of EM65567 can accept inputs of SDA and SCL in the state of chip select (CSB="L"). When not in the state of chip select. The internal shift register and counter are reset in the initial condition. Serial data SDA are input sequentially in order of D7 to D0 at the rising of serial clock (SCL) and are converted into 8-bit parallel data (by serial to parallel conversion) at the rising edge of the 8th serial clock, being processed in accordance with the data. The identification whether are serial data inputs (SDA) are display data or control register data is judged by input to RS pin. RS = "L": display RAM data RS = "H": control register data After completing 8-bit data transferring, or when making no access, be sure to set serial clock input (SCL) to "L". Cares of SDA and SCL signals against external noise should be taken in board wiring. To prevent transfer error due to external noise, release chip select (CSB = "H") every completion of 8-bit data transferring. * This specification is subject to be changed without notice. 19 2003/1/9 (V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
When serial interface is used, access is only made for 8-bit data transfer.
CSB RS SDA SCL
1 2 3 4 5 6 7 8
valid
D7 D6 D5 D4 D3 D2 D1 D0
Figure 4. Serial Interface 7.2 Data write to Display RAM and Control Register The data write to display RAM and Control Register use almost same procedure, only different setting of RS that select access object. RS = "L": Display RAM data RS = "H": Control register data written at the falling edge of signal E. Data write operation
In the case of the 80-family MPU, the data is written at the rising edge of WRB. In the case of the 68-family MPU, the datais
D 0~D 7 (D 0~D 15) W RB RS
W rie to w hich
lim re P
Data0 Data1 Data2
ry a in
Data3 Data4
W rie to control register
W rie to display R AM
Figure 6. Data write operation
7.3 Internal Register Read In the case of display RAM read operation, need dummy read one time. The designated address data are not output to read operation immediately after the address set to AX or AY register, but are output when the second data read. Dummy read is always required one time after address set and write cycle. Read display RAM operation
W RB D 0~D 7 (D 0~D 15) RDB RS
n
Address set (AX,AY) Address = n
***
Dummy Read
n
Data Read Address=n
n+1
Data Read Address=n+1
n+2
Data Read Address=n+2
Figure 7. Read display RAM operation
* This specification is subject to be changed without notice.
20
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
The EM65567 can be read the control registers, in case of control register read operation, data bus upper nibble (D3-D0) use for register address (0 to FH). In maximum, 16 registers can access directly. But number of register is more than 16 registers. Therefore, EM65567 has register bank control. The RE register is set bank number to access. And the RE address is 0FH, in any bank can access RE register. It is need 4-steps to read the specific register in maximum case. (1) Write 04H to RE register for access to RA register. (2) Writes specific register address to RA register. (3) Write specific register bank to RE register. (4) Read specific register contents. Register read operation
W RB D 0~D 7
04H
Bank number write to RE for RA
addr
Address write to RA
bank
Bank number write to RE
RDB
7.4 16-bit Data Access to Display RAM
The EM65567 correspond to 8-bits and 16-bits bus size access. The data bus size can select by WLS register. WLS = "0": 8-bits bus size WLS = "1": 16-bits bus size
In the 16-bits access mode, access for control register use low-byte data bus (D7~D0). Then high byte data bus (D15~D8) are not used in internal circuit. When read control register using 16-bits bus. Register values output to D3-D0 and D15-D4 output "H". 16-bit access is only effective for access to the display RAM. 7.5 Display Start Address Register This register determines the Y-address of the display RAM corresponding to the display start line. The display RAM data that addressed Display Start Address register output to common driver start line. The actual common start line of LCD panel depend on Display Start Common register and SHIFT bit of Display Control register. The register are preset every timing of FLM signal variation in the display line counter. The line counter counts up being synchronized with LP input and generates line addresses which read out sequentially 288 bits data from display RAM to LCD drive circuit. 7.6 Addressing of Display RAM The EM65567 has built-in bit mapped display RAM. The display RAM consists of 768 bits (8 bits*96) in the X-direction and 66 bits in the Y-direction. In the gradation display mode, the EM65567 provides segment driver output for 8-gradation display using 3 bits and that for 4-gradation display using 2 bits. The three outputs of the segment driver can be used for one pixel of RGB. When connected to an STN color LCD panel, the EM65567 can display 96*66 pixels with 256 colors (8 * This specification is subject to be changed without notice. 21 2003/1/9 (V0.1)
lim re P
RS
Figure 8. Register read operation
ry a in
data
read specific register
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
gradation * 8 gradation * 4 gradation). The address area in the X-direction depends on the access bus size. When use 8-bits bus size, can access 00H to 5FH address. When use 16-bits bus size, can access 00H to 2FH address. In the X-direction, X Address register use to access; and in the Y-direction, Y Address register use to access. Do not specify any address outside the effective address area in each access mode because it is not permitted. In Gradation Display Mode (MON="0") 8-bits bus size access X-address 0H 1H ----------------------------------------------------------------- 5EH 5FH 0H 8bit 8bit 8bit 8bit ---------------41H 8bit 8bit 41H 16bit
Y-address
16-bits bus size access
X-address 0H --------------------------------------------------------------------- 2FH 0H 16bit 16bit -------------------------------
Y-address
lim re P
ry a in
8bit 8bit 16bit
In the monochrome display mode, can access 288*66dots size two screens (plane 0/plane 1). The selection of either plane 0 or 1 to access is made by the plane selection register (PSEL). The address area in the X-direction depends on the access bus size. When use 8-bits bus size, can access 00H to 23H address. When use 16-bits bus size, can access 00H to 11H address. In Monochrome Display Mode (MON="1") 8-bits bus size access X-address 0H 1H ----------------------------------------------------------------- 22H 23H 0H 8bit 8bit 8bit 8bit
8bit
Y-address
Plane 0 41H 8bit8bit 8bit 8bit
0H 1H
Plane 1
8bit 8bit8bit 8bit -------------------------------------------------------------- 22H 23H
* This specification is subject to be changed without notice.
22
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
16-bits bus size access X-address 0H --------------------------------------------------------------------- 11H 0H 16bit 16bit ---------------41H 16bit
Plane 1 16bit 0H -----------------------------------------------------------------16bit 11H 16bit
Y-address
Plane 0 16bit
The addresses, X Address and Y Address are possible to be set up so that they can increment automatically with the address control register. The increment is made every time display RAM is read or written from MPU. In the Y-direction, 288 bits of data are read out to the display data latch circuit by internal operation when the LP rises in a one-line cycle. They are output from the display data latch circuit when the LP fails. When FLM signals being output in one frame cycle are at "H", the values in the display starting line register are preset in the line counter and the line counter counts up at the falling of LP signals. The display line address counter is synchronized with each timing signal of the LCD system to operate and is independent of address counters X and Y.
7.7 Display RAM Data and LCD (only monochrome mode) as follows.
One bit of display RAM data corresponds to one dot of LCD. Normal display and reverse display by REV register are set up Normal display (REV=0): RAM data = "0" not lighted RAM data = "1" lighted Reverse display (REV=1): RAM data = "0" lighted RAM data = "1" not lighted 7.8 Segment Display Output Order/Reverse Set up The order of display output, SEGA0, SEGB0, SEGC0 to SEGA95, SEGB95, and SEGC95 can be reversed. If REF control bit set to "1", display by reversing access to display RAM from MPU by using REF register, lessen the limitation in placing IC when assembling an LCD panel module.
lim re P
ry a in
* This specification is subject to be changed without notice.
23
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
7.9 Relationship between Display RAM and Address The Display RAM block diagram shows in the figure below:
Bit-order reverse W rite:depend on REF,SW AP Read:depend on REF
Internal Data Bus
G rayscale Conv ersion
SEGMENT O utput I/F Data conversion is depend on MON, DSEL, REF,SW AP,GLSB
Display start address
Bit order rev erse
Read Data
Data Conv ersion
Segm ent data
W rite Data
Effective Y address
Display RAM
X-Address (00H~5FH)
Effective X address
Address conv ersion circuit
MPU I/F
The EM65567 execute address conversion that depends on control register setting. In case of auto increment mode, usually AX register is added one. For instance when REF and AXI are both "1", AX register is added one, but effective X address seems decrement because of address conversion. The effective Y address use AY register values as it is.
lim re P
AX Register
Figure 10. The Display RAM block diagram
ry a in
Address conversion is depend on MON,W LS, PSEL,REF setting Valid maximum is depend on MO N,W LS setting
* This specification is subject to be changed without notice.
LA Register
AY Register
Y-Address (00H~41H)
Counter
24
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(1) Monochrome mode, 8-bits Access mode, Display Start Address = "00H" and Plane0 or Plane1 displayed.
X Address REF=1 REF=0 Note 1 Note 2 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH -----------39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H SEGA0(SEG0) SEGB0(SEG1) SEGC0(SEG2) Segment Output X = 23H X = 22H ----X = 00H X = 01H ----D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ----D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 ----X = 00H X = 23H D7 D6 D5 D4 D3 D2 D1 D0 D0 D1 D2 D3 D4 D5 D6 D7 Y Address Common Output
Display Start Line
-----
lim re P
--------SEGB1(SEG4) SEGC1(SEG5) SEGA2(SEG6) SEGB2(SEG7) SEGC2(SEG8) SEGA3(SEG9) SEGB3(SEG10) SEGC3(SEG11) SEGA4(SEG12) SEGB4(SEG13) SEGC4(SEG14) SEGA5(SEG15) SEGB93(SEG280) SEGC93(SEG281) -----
ry a in
-----------39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H -----------COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMA COMB -----------SEGB94(SEG283) SEGC94(SEG284) SEGA95(SEG285) SEGB95(SEG286) SEGC95(SEG287)
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15
Line Add
------------
Note 1: (REF, SWAP) = (1,0) or (0,1) Note 2: (REF, SWAP) = (1,1) or (0,0)
* This specification is subject to be changed without notice.
SEGA1(SEG3)
SEGA94(SEG282)
25
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(2) Monochrome mode, 16-bits Access mode, Display Start Address = "00H" and Plane0 or Plane1 displayed.
X Address REF=1 REF=0 Note 1 Note 2 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH -----------39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H SEGA0(SEG0) SEGB0(SEG1) SEGC0(SEG2) Segment Output X = 11H ----X = 00H ----D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 ----D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 ----X = 00H X = 11H D15 D14 D13 ----D0 D1 D2 ----Y Address
-----
-----
lim re P
--------SEGB1(SEG4) SEGC1(SEG5) SEGA2(SEG6) SEGB2(SEG7) SEGC2(SEG8) SEGA3(SEG9) SEGB3(SEG10) SEGC3(SEG11) SEGA4(SEG12) SEGB4(SEG13) SEGC4(SEG14) SEGA5(SEG15) SEGB93(SEG280) SEGC93(SEG281) -----
ry a in
--------------------------39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H -----------COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMA COMB -----------SEGB94(SEG283) SEGC94(SEG284) SEGA95(SEG285) SEGB95(SEG286) SEGC95(SEG287)
Common Output D2 D1 D0 Display Start Line D13 D14 D15 00H COM0 01H COM1 02H COM2 03H COM3 04H COM4 05H COM5 06H COM6 07H COM7 08H COM8 09H COM9 0AH COM10 0BH COM11 0CH COM12 0DH COM13 0EH COM14 0FH COM15 Line Add
------------
------------
Note 1: (REF, SWAP) = (1,0) or (0,1) Note 2: (REF, SWAP) = (1,1) or (0,0)
* This specification is subject to be changed without notice.
SEGA1(SEG3)
SEGA94(SEG282)
26
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(3) Gradation mode, 8 bits access mode, (REF, SWAP) = (0,0)
X Address X = 00H X = 01H ----- X = 5FH D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 ----- D0 D1 D2 D3 D4 D5 D6 D7 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH -----------39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H SEGA0(SEG0) Segment Output SEGB0(SEG1) SEGC0(SEG2) -----------Y Address
Common Output
Display Start Line
-----
-----
lim re P
----SEGA1(SEG3) SEGB1(SEG4) SEGC1(SEG5) SEGA95(SEG285) -----
ry a in
-----------39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H -----------COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMA COMB -----------SEGB95(SEG286) SEGC95(SEG287)
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15
Line Add
* This specification is subject to be changed without notice.
27
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(4) Gradation mode, 16 bits access mode, (REF, SWAP) = (0,0)
X Address X = 00H ----- X =2FH D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 ----- D0 D1 ----00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH -----------39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H SEGA0(SEG0) Segment Output SEGB0(SEG1) SEGC0(SEG2) -----------Y Address
Common Output D13 D14 D15 Display Start Line 00H COM0 01H COM1 02H COM2 03H COM3 04H COM4 05H COM5 06H COM6 07H COM7 08H COM8 09H COM9 0AH COM10 0BH COM11 0CH COM12 0DH COM13 0EH COM14 0FH COM15 Line Add ----------------------------------
-----
-----
-----
-----
lim re P
----SEGA1(SEG3) SEGB1(SEG4) SEGC1(SEG5) SEGA94(SEG282) -----
-----
ry a in
39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H COM57 COM58 COM59 COM60 COM61 COM62 COM63 COMA COMB SEGC95(SEG287)
------------
-----
7.10 Monochrome Two-Plane Display When the gradation display is not necessary, the monochrome display may be selected. In this case, display RAM for gradation are can be used to select either of two planes for display. When data is written to the memory, the plane 0 or 1 is selected with the PSEL bit. The DSEL control bit select plane for display, data can be written to the other plane, and when the write has been completed, the displayed plane can be changed. In the monochrome mode (MON="1"), 00H, 01H, ...23H are assigned to X-addresses on the plane 0/1. Access to each plane is changed with the PSEL bit.
* This specification is subject to be changed without notice.
28
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
DSEL Plane 0
Plane 1
PSEL
7.11 Display Data Structure and Gradation Control per output to achieve the gradation display.
For the purpose of gradation control, one pixel requires multiple bits of display RAM. The EM65567 has 3-bit or 2-bit data The three outputs of the segment driver are used for one pixel of RGB, and the EM65567 is connected to an STN color LCD panel. It can display 96*66 pixels with 256 colors (3 bits * 3 bits * 2 bits). In this case, since the gradation display data is processed by a single access to the memory, the data can be rewritten fast and naturally. written to the display RAM. The weighting for each data bit is dependent on the status of the SWAP bit and the REF bit that is selected when data is
(REF, SWAP)=(0,0) or (1,1)
lim re P
SEGAi SEGBi palette Aj palette Bj 0 0
M SB
ry a in
i=0 to 95 Gradation palette j=0 to 7 Gradation control
SEGCi
palette Cj
0 Gradation LSB circuit
1
LSB
0
0
M SB
1
LSB
1
1
M SB
display RAM data
0 D0
0 D1
1 D2
0 D3
0 D4
1 D5
1 D6
1 D7
MPU write data X address: nH
Note : Internal X address : nH : 5FH-nH
(REF="0") (REF="1")
* This specification is subject to be changed without notice.
29
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(REF, SWAP)=(0,1) or (1,0)
SEGAi
SEGBi
SEGCi
i=0 to 95
palette Cj
palette Bj
palette Aj
Gradation palette j=0 to 7
Gradation control
Gradation LSB circuit
display RAM data
1
M SB
1
1
LSB
0
M SB
0
1
LSB
0
M SB
0
0
0 D0
0 D1
1 D2
0 D3
0 D4
1 D5
D6
Note : Internal X address : nH
In 16-bits access, the weighting for each data bit is dependent on the status of the SWAP bit and the REF bit that is selected when data is written to the display RAM, as in the case with 8-bits access. (REF, SWAP)=(0,0) or (1,1)
SEGAi
lim re P
SEGBi SEGCi SEGAi+1 palette Bj palette Cj palette Aj 0 1
LSB
ry a in
1 1 D7 (REF="0") : 5FH-nH (REF="1")
SEGBi+1 SEGCi+1 palette Bj palette Cj
MPU write data X address: nH
i=0, 2, 4 to 94
palette Aj
Gradation palette j=0 to 7 Gradation control
0 Gradation LSB circuit 0 0 0
M SB
1
LSB
1
1
M SB
0
0
M SB
1
LSB
0
0
M SB
1
LSB
1
1
M SB
display RAM data
M SB
0 D0
0 D1
1 D2
0 D3
0 D4
1 D5
1 D6
1 D7
0 D8
0 D9
1 D10
0 D11
0 D12
1 D13
1 D14
1 D15
MPU write data X address: nH
Note : Internal X address : nH : 2FH-nH
(REF="0") (REF="1")
* This specification is subject to be changed without notice.
30
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(REF, SWAP)=(0,1) or (1,0)
SEGAi SEGBi SEGCi SEGAi+1 SEGBi+1 SEGCi+1
i=0, 2, 4 to 94
palette Cj
palette Bj
palette Aj
palette Cj
palette Bj
palette Aj
Gradation palette j=0 to 7
Gradation control display RAM data
0 1
M SB
1
1
LSB
0
M SB
0
1
LSB
0
M SB
0
1
M SB
1
1
LSB
0
M SB
0
1
LSB
0
M SB
0
Gradation LSB circuit
0 D0
0 D1
1 D2
0 D3
0 D4
1 D5
1 D6
1 D7
0 D8
0 D9
1 D10
0 D11
0 D12
1 D13
1 D14
1 D15
Note : Internal X address : nH : 2FH-nH
(REF="0") (REF="1")
7.12 Gradation LSB Control
In the gradation display mode, the EM65567 provides segment driver output for 8 gradation display using 3-bits and that for 4 gradation display using 2-bits. The segment driver output for the 4-gradation display uses 2-bits written to the corresponding RAM area and 1-bit supplemented by the gradation LSB circuit, and then selects 4-gradation form 8-gradation. In the gradation display mode, the segment driver output for the 4-gradation display result in a gradation level of 0 regardless of the gradation LSB, when 2-bits of data on the display RAM are "00". When 2-bits of data on the display RAM is "11", a gradation level of 7/7 is selected regardless of the bit information of the gradation LS8.The other gradation levels are selected depending on 2-bits of data on the display RAM and the gradation LSB bits. One bit of data is supplemented by setting the gradation LSB register (GLSB). The Gradation LSB control bit applied to all 4-gradation segment drivers. Gradation LSB = "0": Selects 0 as the LSB information on the RAM for 4-gradation segment drivers. Gradation LSB = "1": Selects 1 as the LSB information on the RAM for 4-gradation segment drivers. 7.13Gradation Palette The EM65567 has two gradation display modes, the gradation fixed display mode and the gradation variable display mode. Select either of the two modes using the gradation display mode register. PWM = "0": Selects the variable display mode using 8 gradation selected from 32 gradation. PWM = "1": Selects the fixed display mode using specific 8 gradation. To select the best gradation level suited to the LCD panel, use the gradation palette register among the 32-level gradation palettes in the gradation variable display mode. The segment driver output is set up by the selected 8-levels of gradation palettes. The gradation palette register provides three registers for the SEGAi (0-95) group, SEGBi (0-95) group, and SEGCi (0-95) * This specification is subject to be changed without notice. 31 2003/1/9 (V0.1)
lim re P
ry a in
MPU write data X address: nH
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
group of segment driver outputs [palettes Aj, Bj, and Cj (j = 0-7)]. Each register consists of a 5-bit register, selecting 8-gradations from the pattern for 32-gradations. Initial values on gradation palette register [Three groups of palettes Aj, Bj, and Cj (j = 0-7) are available]
(MSB)RAM data(LSB) 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 Register Name Initial value Gradation Palette 0 0 0 0 0 0 Gradation Palette 1 0 0 1 0 1 Gradation Palette 2 0 1 0 1 0 Gradation Palette 3 0 1 1 1 0 Gradation Palette 4 1 0 0 0 1 Gradation Palette 5 1 0 1 0 1 Gradation Palette 6 1 1 0 1 0 Gradation Palette 7 1 1 1 1 1
Gradation level table (PWM = "0", variable mode) [Three groups of palettes Aj, Bj, and Cj (j = 0-7) are available
Palette
Gradation Gradaton Remarks Palette level level 00000 0 gradation palette0 initial valu1 0 0 0 0 16/31 0000 00010 0001 00100 0010 00110 0011 01000 0100 0101 0110 1/31 2/31 4/31 6/31 8/31 3/31
5/31
7//31 9/31
lim re P
1 0 0 0 1 17/31 1 0 0 1 1 19/31
1 0 0 1 0 18/31 1 0 1 0 0 20/31
ry a in
Remarks gradation palette4 initial value gradation palette5 initial value gradation palette6 initial value gradation palette7 initial value
gradation palette1 initial valu1 0 1 0 1 21/31 1 0 1 1 0 22/31 1 0 1 1 1 23/31 1 1 0 0 0 24/31 1 1 0 0 1 25/31
0 1 0 1 0 10/31 11/31 13/31 0 1 1 0 0 12/31 0 1 1 1 0 14/31 0 1 1 1 0 15/31
gradation palette2 initial valu1 1 0 1 0 26/31 1 1 0 1 1 27/31 1 1 1 0 0 28/31 1 1 1 0 1 29/31 gradation palette3 initial valu1 1 1 1 0 30/31 1 1 1 1 1 31/31
Gradation level table (PWM = "1", fixed mode)
(MSB)RAM data(LSB) Gradation level 0 0 0 0 0 0 1 1/7 0 1 0 2/7 0 1 1 3/7 1 0 0 4/7 1 0 1 5/7 1 1 0 6/7 1 1 1 7/7 RAM Data GLSB Gradation level 0 0 0 0 1 0 2/7 0 1 1 3/7 1 0 0 4/7 1 0 1 5/7 1 1 7/7 Don't Care
* This specification is subject to be changed without notice.
32
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
7.14 Display Timing Circuit The display timing circuit generates internal signals and timing pulses (LP, FLM, M and CLK) by clock. It can select external input (CK) or internal oscillation. By setting up Master/Slave mode (M/S), the state of timing pulse pins and the timing generator changes.
M/S Pin Mode LP Pin M Pin FLM Pin CLK Pin L Slave Input Input Input Input H Master Output Output Output Output State of timing generator LP,FLM,M generation stop Operation state
Display timing pulse pins and Generator State 7.15 Signal Generation to Display Line Counter, and Display Data Latching Circuit Both the clock to the line counter and clock to display data latching circuit from the display clock (LP) are generated. Synchronized with the display clock (LP), the line addresses of Display RAM are generated and 288-bits display data are latched to display data latching circuit to output to the LCD drive circuit (Segment outputs). Read-out of the display data to the LCD drive circuit is completely independent of MPU. Therefore, MPU that has no relationship the read-out operation of the display data can access.
7.16 Generation of the Alternated Signal (M) and the Synchronous Signal (FLM)
LCD alternated signal (M) and synchronous signal (FLM) are generated by the display clock (LP). The FLM generates alternated drive waveform to the LCD drive circuit. Normally, the FLM generates alternated drive waveform every frame (M-signal level is reversed every one frame). However, by setting up data (n-1) in an n-line reverse register and n-line alternated control bit (NLIN) at "1", n-line reverse waveform is generated. When the EM65567 is used in multi chip system, master chip must provide LP, FLM, and M signals for the slave chip. 7.17 Display Data Latching Circuit
Display data latching Circuit temporally latches display data that is output display data to LCD driver circuit from display RAM every one common period. Normal display/reverse display, display ON/OFF, and display all on functions are operated by controlling data in display data latch. Therefore, no data within display RAM changes. 7.18 Output Timing of LCD Driver Display timing at Normal mode (not reverse mode), 1/66 DUTY, and on monochrome mode.
lim re P
ry a in
* This specification is subject to be changed without notice.
33
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
65 LP FLM M
66
1
2
3
66
1
2
3
66
1
COM0
COM1
SEG0
SEG1
7.19 LCD Drive Circuit
This drive circuit generates four levels LCD drive voltage. The circuit has 288 segment outputs and 66 common outputs and outputs combined display data and M signal. Two of common outputs, COMA and COMB, are special outputs. The COMA and COMB outputs be not influenced by partial setting. Mainly use for display. The common drive circuit that has shift register sequentially outputs common scan signals. 7.20 Oscillating Circuit The EM65567 has the CR oscillator. The output from this oscillator is used as the timing signal source of the display and the boosting clock to the booster. This can use only in the master operation mode. When in the master operation mode and external clock is used, feed the clock to CK pin. The duty cycle of the external clock must be 50%. The resistance ratio of CR oscillator is programmable. If change this ratio, also change frame frequency for display. 7.21 Power Supply Circuit This circuit supplies voltages necessary to drive a LCD. The circuit consists of booster and voltage converter. Boosted voltage from the booster is fed to the voltage converter that converts this input voltage into V0, V1, V2, V3 and V4 that are used to drive the LCD. This internal power supply should not be used to drive a large LCD panel containing many * This specification is subject to be changed without notice. 34 2003/1/9 (V0.1)
lim re P
ry a in
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
pixels. Otherwise, display quality will degrade considerably. Instead, use an external power supply. When using the external power supply, turn off the internal power supply (AMPON, DCON="00"), disconnect pins CAP1+, CAP2+, CAP2-, CAP3+, CAP3-, VOUT, VEE, VREF and VREG. Then, feed external LCD drive voltages to pins V0, V1, V2, V3 and V4. The power circuit can be control by power circuit related register. So partial function of built-in power circuit can use with external power supply.
DCON AMPON Booster circuit Voltage conversion circuit 0 0 1 0 1 1 DISABLE DISABLE ENABLE DISABLE ENABLE ENABLE Extemal voltage input V0,V1,V2,V3 and V4 are supplied VOUT is supplied Note 1 2 -
1 Because the booster and voltage converter not operating, disconnect pins CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, CAP3-, VOUT, VEE, VREG and VREF. Apply external LCD drive voltages to corresponding pin. 2 Because the booster is not operating, disconnect pins CAP1+, CAP1-, CAP2+, CPA2-, CAP3+, CAP3Input the reference voltage at VREF pin. 7.22 Booster Circuit
Derive the voltage source to be supplied to the voltage converter from VOUT pin and then
Placing capacitor C1 across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP3- and across VOUT and VSS boosts the voltage coming from VEE and VSS n-times and outputs the boosted voltage to VOUT pin. The twice, third, or fourth boosted voltage output to the VOUT pin by the boost step register set. The boost step registers set by the command. (1) In case of using only twice boosted voltage, placing C1 only across CAP1+ and CAP1- and opening CAP2+, CAP2-, CAP3+, CAP3 (2) In case of using only third boosted voltage, placing C1 only across CAP1+ and CAP1-, across CAP2+ and CAP2- and opening CAP3+, CAP3(3) In case of using only fourth boosted voltage, placing C1 only across CAP1+ and CAP1-, across CAP2+ and CAP2-, across CAP3+ and CAP3When use built-in booster circuit, output voltage (VOUT) must less than recommended operating voltage (15.0 Volt). If output voltage (VOUT) over recommended operating voltage, correct work of chip can not guarantee.
lim re P
VOUT=9 V
ry a in
VEE=3V
VEE=3V
VSS=0V 3 times boostng
VSS=0V 4 times boostng
* This specification is subject to be changed without notice.
35
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
7.23 Electronic volume The voltage conversion circuit has built-in an electronic volume, which allows the LCD drive voltage level V0 to be controlled with DV register setting and allows the tone of LCD to be controlled. The DV registers are 7-bits, so can select 128 voltage values for the LCD drive voltage V0. 7.24 Voltage Regulator The EM65567 has built-in reference voltage regulator, which generate the voltage amplified by input voltage from VREF pin. The generated voltage is output at the VREG pin. Even if the boosted voltage level fluctuates, VREG remains stable so far as VOUT is higher than VREG Stable power supply can be obtained using this constant voltage, even if the load fluctuates. The EM65567 uses the generated VREG level for the reference level of the electronic volume to generate LCD drive voltage. In order to stabilize the output voltage at the VREG pin, connect the capacitor C3 as appropriate by choosing its value. 7.25 LCD Drive Voltage Generation Circuit
The voltage converter contains the voltage generation circuit. The LCD drive voltages other than V0, that is, V1, V2, V3 and V4 are obtained by dividing V0 through a resistor network. The LCD drive voltage from EM65567 is biased at 1/5, 1/6, 1/7, 1/8 or 1/9. When using the internal power supply, connect a stabilizing capacitor C2 to each of pins V0 to V4. The capacitance of C2 should be determined while observing the LCD panel to be used. When using the external power supply, apply external LCD drive voltages to V0, V1, V2, V3, V4, disconnect pins CAP1+, CAP-, CAP2+, CAP2-, CAP3+, CAP3-, VOUT, VEE, VREF and VREG. When using only the voltage conversion circuit, turn off the internal booster circuit, disconnect pins CAP1+, CAP1-, CAP2+, CAP2-, CAP3+, CAP3- and VEE. Derive the voltage source to be supplied to the voltage converter from VOUT pin and then input the reference voltage to VREF pin.
lim re P
ry a in
* This specification is subject to be changed without notice.
36
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
VDD VDD VEE VREF VREG v ss CAP1CAP1+ CAP2CAP2+ CAP3CAP3+ C3
VDD VDD VEE VREF VREG C1 C1 C1 CAP1CAP1+ CAP2CAP2+ CAP3CAP3+
VO UT V0 V0 V1 V2 V3 V4
External V1 Power V2 Supply V3
lim re P
V4
v ss
ry a in
C1 VO UT V0 V1 V2 V3 V4 C2 C2 C2 C2 C2
v ss
When using external power supply.
When using internal power circuit. (4 times boosting)
Recommended value.
C1 C2 C3 1.0 to 4.7 F 1.0 to 2.2 F 0.1 F
Note: External Capacitance must be use B characteristic.
* This specification is subject to be changed without notice.
37
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
VDD VDD VEE VREF VREG C3 v ss C1 C1 C1 CAP1CAP1+ CAP2CAP2+ CAP3CAP3+
Thermisto r
VDD VDD VEE VREF VREG C3 v ss C1 C1 C1 CAP1CAP1+ CAP2CAP2+ CAP3CAP3+
C1 v ss VO UT V0 V1 V2 V3 V4
v ss
When using internal power circuit with external reference voltage input. (4 times boosting)
lim re P
C2 C2 C2 C2 C2
ry a in
C1 v ss VO UT V0 V1 V2 V3 V4 C2 C2 C2 C2 C2 v ss
When using internal power circuit with thermistor for temperature independt. (4 times boosting)
Recommended value.
C1 C2 C3 1.0 to 4.7 F 1.0 to 2.2 F 0.1 F
Note: External Capacitance must be use B characteristic.
* This specification is subject to be changed without notice.
38
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
VDD VDD VEE VREF C3 v ss VREG CAP1CAP1+ CAP2CAP2+ CAP3CAP3+
External Power Supply C2 C2 C2 C2 C2
VO UT V0 V1 V2 V3 V4
Recommended value.
C2 C3
lim re P
v ss
ry a in
When using internal power circuit.
(VOUT supplied from external, no use boosting circuit)
1.0 to 2.2 F 0.1 f
Note: External Capacitance must be use B characteristic.
* This specification is subject to be changed without notice.
39
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
7.26 Partial Display Function The EM65567 has the partial display function, which can display a part of graphic display area. This function is used be set lower bias ratio, lower boost step, and lower LCD drive voltage. Since setting partial display function, EM65567 provides low power consumption. Partial display function is the most suitable for clock indication or calendar indication when a portable equipment stand-by.
ELAN LCD DRIVER Low Power and Low Voltage Normal Display Image of partial Display LCD DRIVER
When using the partial display function, it is necessary to keep following sequence.
lim re P
Partial Display
Any display condition
Display off (ON/OFF= "0")
Power circuit off (DCON= "0", AM PON= "0") W ait for m ore than 200m s
ry a in
Partial Display
Setting Power Function * Boost step set * Electronic volum e set * Bias Ratio set
Power circuit on (DCON= "1", AM PON= "1") W ait for m ore than 200m s
Setting Display Function * Duty Ratio set * Display start Address * Display start com m on
Display on (ON/OFF= "1")
Select a display duty ratio for the partial display from 1/10, 1/18, 1/26, 1/34, 1/42, 1/50 and 1/58 using the DS(LCD duty ratio) register. Set the most suitable values for LCD drive bias ratio, LCD drive voltage, electronic volume, the number of boosting steps, and others according to the actually used LCD panel and the selected duty ratio. * This specification is subject to be changed without notice. 40 2003/1/9 (V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
7.27 Discharge circuit The EM65567 has built-in the discharge circuit, which discharges electricity from capacitors for a stability of power sources(V0~V4). The discharge circuit is valid, while the DIS register is set to "1" or the RESB pin is set "L". When the built-in power supply is used, should be set DIS="1" after the power source is turned off (DCON, AMPON)=(0, 0). And don't turn on both the built-in power source and the external power source (V0~V4, VOUT) while DIS="1". 7.28 Initialization The EM65567 is initialized by setting RESB pin to "L". Normally, RESB pin is initialized together with MPU by connecting to the reset pin of MPU. When power ON, be sure to make RESB="L".
Display RAM X Address Y Address Display starting line Display ON/OFF Display Normal/Reverse Display duty n-line alternated Common shift direction Increment mode REF mode Data SWAP Mode Register in electronic volume Power Supply Display mode Bias ratio Gradation palette 0 Gradation palette 1 Gradation palette 2 Gradation palette 3 Gradation palette 4 Gradation palette 5 Gradation palette 6 Gradation palette 7 Gradation display mode Gradation LSB RAM access data length Discharge Register Booster frequency Static Pictograh
lim re P
Not fixed 00H set 00H set Set at the first line(0H) Display OFF Normal 1/66 every frame unit COMOCOM63, COMA, COMB Increment OFF Normal OFF (0,0,0,0,0,0,0) OFF Gradation display mode 1/9 bias (0, 0, 0, 0, 0) (0, 0, 1, 0, 1) (0, 1, 0, 1, 0) (0, 1, 1, 1, 0) (1, 0, 0, 0, 1) (1, 0, 1, 0, 1) (1, 1, 0, 1, 0) (1, 1, 1, 1, 1) Variable mode "0" 8-bits mode "0" (0,0) OFF
ry a in
* This specification is subject to be changed without notice.
41
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
7.29 Precaution when Power ON and Power OFF This LSI may be permanently damaged by high current that may flow if a voltage is supplied to the LCD driver power supply while the system power supply is floating. The detail is as follows. ( i )When using as external power supply * Procedure for Power ON (1) Logic system (VDD) power ON, make reset operation. (2) Supply external LCD drive voltage to corresponding pins (V0, V1, V2, V3 and V4) * Procedure for Power OFF (1) Set HALT register to "1" or make reset operation. (2) Cut off external LCD drive voltage. (3) Logic system(VDD) power OFF.
Note: connect the serial resistor (50 to 100) or fuse to the LCD drive power V0 or VOUT(when only use internal voltage conversion circuit) of the system as a current limiter. Moreover, set up the suitable value of the resistor in consideration of LCD display grade.
( ii )When using the built-in power supply * Procedure for Power ON (1) Logic system (VDD) power ON
(2) Booster circuit system (VEE) power ON
(3) Make reset operation, booster and voltage conversion circuit enable. If VDD and VEE voltages aren't same potential, power on logic system (VDD) first. * Procedure for Power OFF (1) Set HALT register to "1" or make reset operation. (2) Booster circuit system (VEE) power ON (3) Logic system (VDD) power OFF. If VDD and VEE are not same potential, cut off VEE first. After VEE, VOUT, V0, V1, V2, V3 and V4 voltages are below LCD ON voltage (threshold voltage for Liquid crystal turn on), power off logic system (VDD). ( iii )Power supply rising time Though especially there is no constraint on the rising time of the power supply, the tr (rising time) of the following is recommended in the practical use.
lim re P
ry a in
* This specification is subject to be changed without notice.
42
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
VDD,VEE tr
Item tr
Recommended rising time 30us ~ 10ms
Applicable Power VDD, VEE
Note: The rising time is the time from 10% of VDD, VEE to 90%.
7.30 Example of Setting Registers
(1) Initialization
Power ON (VDD,VEE-VSS)
lim re P
RESET
Power will stable
ry a in
W ait for more than 50ms
Setting Operational Functions * Electrical volume set * Bias Ratio set
Setting Operational Functions * Setting power control (DCON= "1", AM PON= "1")
End of initialization
If VDD and VEE voltage are not same, connect the logic system power supply (VDD) first.
* This specification is subject to be changed without notice.
43
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(2) Display data
End of initialization
* * * *
Setting Operational Functions Setting display start address Setting address increment control Setting X address Setting Y address
Setting Operational Functions * W rite dsiplay data
(3) Power OFF
lim re P
Any condition
Setting Operational Functions * Setting display on/off control (ON/OFF= "1")
End of initialization
ry a in
Setting Operational Functions * Setting HALT= "1" or make reset operation (LCD driver output VSS level) * Setting DIS= "1" (Discharge V0-V4 capacitor)
W ait for more than 100 ms
Power OFF ( VEE,VDD)
When turning off the power, set HALT command or make reset operation. If VDD and VEE voltage are not same, disconnect the booster circuit power supply (VEE) first.
* This specification is subject to be changed without notice.
44
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
PROGRAM EXAMPLES
Use Elan Risc II MCU assembly
;***************************************************************************** ; INITIALIZATION SETTING EXAMPLE OF EM65567
;***************************************************************************** WRITEOR macro REGSEL,INSDAT MOV OR CALL endm EM65567_INI: WRITEOR #REREGISTERSET,#0b00000000 WRITEOR #POWERCONTROL,#0b00000001 MOV CALL A,#50 WAIT_A_MS ;BOOSTER x 4 (B1 ,B0 = 1 1) ;SET RE FLAG 000--> INSTRUCTION bank 0 ;ACL(B0) =1 initialization ON A,INSDAT A,REGSEL WRITE_LCD_1BYTE ; Write macro ; Write data ; Write register address ;Write A to LCD
;WAIT 50ms FOR EM65567 INITIAL SETTING
WRITEOR #BOOSTERSET,#0b00000011
WRITEOR #POWERCONTROL,#0b00001010
WRITEOR #BIASRATIOCONTROL,#0b00000000 WRITEOR #LCDDUTYSET,#0b00000111
WRITEOR #INCREMENTCONTROL,#0b00000011 ; X (B0) INCREMENT ; Y(B1) INCREMENT WRITEOR #DISPLAYSTARTLINELOWER,#0b00000000 WRITEOR #DISPLAYSTARTLINEUPPER,#0b00000000 WRITEOR #XADDRESSLOWER,#0b00000000 WRITEOR #XADDRESSUPPER,#0b00000000 ;SET Display Start LOWER Line=0 ;SET Display Start UPPER Line=0 ;SET X Add=0
lim re P
;BIAS =1/9 (B2,B1,B0=000) ;SET Y Add=0 ;SWAP(B1) = '1'
;BOOSTER CIRCUIT(B1) ON; OPAMP(B3) ON
;LCD Duty Set 1/66 DUTY (B2,B1,B0=111)
ry a in
WRITEOR #YADDRESSLOWER,#0b00000000 WRITEOR #YADDRESSUPPER,#0b00000000 WRITEOR #DISPLAYCONTROL1,#0b00001000 WRITEOR #DISPLAYCONTROL2,#0b00000010
;DISPLAY(B0) OFF ; SHIFT(B3) = '1'
WRITEOR #REREGISTERSET,#0b00000100 ;SET RE FLAG 100--> INSTRUCTION bank 4 WRITEOR #ELECTRONICVOLUMEUPPER,#0b00000111 WRITEOR #ELECTRONICVOLUMELOWER,#0b00001111 WRITEOR #COMMONSTARTLINESET,#0b00000100 ;SET ELECTRONIC UPPER TO MAX 0111 ;SET ELECTRONIC LOWER TO MAX 1111 ;SET COMMON START FROM COM 32 B2='1'
WRITEOR #STATICPICTGRAPHCONTROL,#0b00000000 ;Static Pictograph Control =000 WRITEOR #DISPLAYSELECTCONTROL,#0b00001000 WRITEOR #RAMDATALENGTHSET,#0b00000000 WRITEOR #DISCHARGECONTROL,#0b00000010 WRITEOR #REREGISTERSET,#0b00000000 RET ;PWM (B3)=1 8-gradation fixed display ;WLS=0(B0) 8-BIT WIDTH MODE ;Discharge(B0) off; High power mode(B1) off ;SET RE FLAG 000--> INSTRUCTION bank 0
* This specification is subject to be changed without notice.
45
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
***************************************************************************** ; WRITE DISPLAY_PICTURE DATA INTO DISPLAY DATA RAM OF EM65567
;***************************************************************************** DATA_WRITE_65567: BS REG_PORTB,F_LCD_A0 ; LCD RS = 1 INSTRUCTION OUTPUT ;SET X Add=0
WRITEOR #XADDRESSLOWER,#0b00000000 WRITEOR #XADDRESSUPPER,#0b00000000 WRITEOR #YADDRESSLOWER,#0b00000000 WRITEOR #YADDRESSUPPER,#0b00000000 MOV MOV DATA_W1: MOV MOV BC DATA_W2: TBRD CALL DEC JBS DEC JBS BS RET A,#LINE_X_MAX DRAMX,A REG_PORTB,F_LCD_A0 A,#LINE_Y_MAX DRAMY,A
;SET Y Add=0
;COMMON = 3FH (63)
;SEGMENT = 5fh (95)
01,REG_ACC
WRITE_LCD_1BYTE DRAMX
REG_STATUS,F_C,DATA_W2 DRAMY
REG_STATUS,F_C,DATA_W1 REG_PORTB,F_LCD_A0
lim re P
;LCD RS = 1 INSTRUCTION OUTPUT
;SET LCD RS=0 DATA READ/WRITE
;WRITE LCD SCREEN FROM DATA INDEX
ry a in
;***************************************************************************** ; WRITE ONE BYTE DATA INTO DDRAM (PARALLEL MODE 80 SERIES)
;***************************************************************************** ;AT FIRST DEFINE A0 TO IDENTIFY DATA OR INSTRUCTION WRITE WRITE_LCD_1BYTE: JBS BC MOV NOP NOP BS NOP NOP REG_PORTC,F_LCD_WR ;SET /WR=1 DISABLE WRITE REG_DCRG,F_LAHEN,WRITE_LCD_1BYTE_1 REG_PORTC,F_LCD_WR REG_DATA,A ;CHECK REG_DCRG LAHEN BIT=1 OR NOT ;SET /WR=0 ENABLE WRITE ;MOVE A==> PORT_G ;Write low pulse( Wait 2 instruction cycles)
* This specification is subject to be changed without notice.
46
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
NOP NOP RET WRITE_LCD_1BYTE_1: MOV RET REG_DATA,A ;MOVE A==> PORT_G
;***************************************************************************** ; ; ; ;***************************************************************************** ;AT FIRST DEFINE A0 TO IDENTIFY DATA OR INSTRUCTION READ READ_LCD_1BYTE: BC NOP NOP MOV NOP BS NOP RET REG_PORTB,F_LCD_RD READ ONE BYTE DATA INTO DDRAM (PARALLEL MODE 80 SERIES)
;SET /RD=0 ENABLE READ
A,REG_DATA
REG_PORTB,F_LCD_RD
lim re P
;MOVE PORT_G ==> A
ry a in
;SET /RD=1 DISABLE READ
* This specification is subject to be changed without notice.
47
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
8. Control Register 8.1 control register
Control Register Table (Bank 0)
Control Register Display Data write Display Data read Internal Register read X Address (Lower nibble) X Address (Upper nibble) Y Address (Lower nibble) Y Address (Upper nibble) Display start address (Lower nibble) Display start address (Upper nibble) n-line altemation (Lower nibble) n-line altemation (Upper nibble) Display control (1) Pins (for 80-family) & Bank CSB RS WRB ROB RE2 RE1 RE0 D7 D6 D5 0 0 0 1 0/1 0/1 0/1 0 0 1 0 0/1 0/1 0/1 0 1 1 0 0/1 0/1 0/1 * * * [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 Address & Code D4 D3 D2 D1 Write Data Read Data * Read Data 0 AX3 1* 0 AY3 1* 0 LA3 1* 0 N3 1* AX2 AX6 AY2 AY6 LA2 * N2 AX1 AX5 AY1 AY5 LA1 LA5 N1 Function Write to Display RAM Read from Display RAM Read out Internal Register Set of X direction Address AX0 in display RAM Set of X direction Address AX4 in display RAM Set of X direction Address AY0 in display RAM Set of X direction Address AY4 in display RAM Set address of display RAM LA0 making common starting line display Set address of display RAM LA4 making common starting line display Set the number of altemated N0 reverse line Set the number of altemated N4 reverse line SHIFT: Select common shift direction MON: Select Monochrome/gradation ON/ ALLON: All display ON OFF ON/OFF: Display ON/OFF control REV: Display normal/reverse NLIN: n line reverse control SWAP: Display data swapping REF REF: Seqment normal/reverse AIM: Select increment mode AXI AYI: Y increment, AXI: X increment AMPON: Intemal AMP. ON HALT: Power saving DCON: Boosting circuit ON ACL ACL: Resetting Set LCD drive duty ratio DS0 Set number of boosting step for VU0 booster circuit Set bias ratio B0 for LCD driving voltage TST0: for LS1 test,must set to "0" RE0 RE: set register bank number D0
[8H] Display control (2)
0
1
0
1
0
0
0
1
0
0
SHI 0 FT
[9H] Increment control Power control
[AH]
[BH] LCD Duty Ratio Booster Bias ratio control Register Access Control
[CH] [DH] [EH] [FH]
Note: The "" mark means "don't care"
lim re P
0 1 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 1 0 1 0* 0 1 0 1 0 0 0 1 0 1 0 1 0 1 0 0 0 1 1 0 0* 0 1 0 1 0 0 0 1 1 0 1* 0 1 0 1 0 0 0 1 1 1 0 1 0 1 0/1 0/1 0/1 1 1 1
SW 1 REV NLIN AP AIM AYI
AMP HA 1 ON LT
ry a in
* N5 ALL MON ON DC ON DS2 * B2 RE2 DS1 VU1 B1 RE1
0* TS 1 T0
Parentheses [ ] shows address for control register.
* This specification is subject to be changed without notice.
48
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
Control Register Table (Bank 1)
Control Register Gradation palette A0 (Lower nibble) Gradation palette A0 (Upper nibble) Gradation palette A1 (Lower nibble) Gradation palette A1 (Upper nibble) Gradation palette A2 (Lower nibble) Gradation palette A2 (Upper nibble) Gradation palette A3 (Lower nibble) Gradation palette A3 (Upper nibble) Gradation palette A4 (Lower nibble) Gradation palette A4 (Upper nibble) Gradation palette A5 (Lower nibble) Gradation palette A5 (Upper nibble) Gradation palette A6 (Lower nibble) Gradation palette A6 (Upper nibble) Register Access Control [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] [8H] [9H] [AH] [BH] [CH] [DH] [FH] Pins (for 80-family) & Bank Address & Code D2 D1 D0 CSB RS WRB ROB RE2 RE1 RE0 D7 D6 D5 D4 D3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0/1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 Function Set the umber of 0 PA03 PA02 PA01 PA00 Gradation Palette A0 Set the umber of 1* * * PA04 Gradation Palette A0 Set the umber of 0 PA13 PA12 PA11 PA10 Gradation Palette A1 Set the umber of 1* * * PA14 Gradation Palette A1 Set the umber of 0 PA23 PA22 PA21 PA20 Gradation Palette A2 Set the umber of 1* * * PA24 Gradation Palette A2 Set the umber of 0 PA33 PA32 PA31 PA30 Gradation Palette A3 Set the umber of 1* * * PA34 Gradation Palette A3 Set the umber of 0 PA43 PA42 PA41 PA40 Gradation Palette A4 Set the umber of 1* * * PA44 Gradation Palette A4 Set the umber of 0 PA53 PA52 PA51 PA50 Gradation Palette A5 Set the umber of 1* * * PA54 Gradation Palette A5 Set the umber of 0 PA63 PA62 PA61 PA60 Gradation Palette A6 Set the umber of 1* * * PA64 Gradation Palette A6 TS TST0: for LS1 test,must set to "0" 1 T0 RE2 RE1 RE0 RE: set register bank number
Note: The "" mark means "don't care"
Parentheses [ ] shows address for control register.
lim re P
ry a in
* This specification is subject to be changed without notice.
49
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
Control Register Table (Bank 2)
Control Register Gradation palette A7 (Lower nibble) Gradation palette A7 (Upper nibble) Gradation palette B0 (Lower nibble) Gradation palette B0 (Upper nibble) Gradation palette B1 (Lower nibble) Gradation palette B1 (Upper nibble) Gradation palette B2 (Lower nibble) Gradation palette B2 (Upper nibble) Gradation palette B3 (Lower nibble) Gradation palette B3 (Upper nibble) Gradation palette B4 (Lower nibble) Gradation palette B4 (Upper nibble) Gradation palette B5 (Lower nibble) Gradation palette B5 (Upper nibble) Register Access Control [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] [8H] [9H] [AH] [BH] [CH] [DH] [FH] Pins (for 80-family) & Bank Address & Code CSB RS WRB ROB RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 D0 Function Set the umber of Gradation Palette A7 Set the umber of Gradation Palette A7 Set the umber of Gradation Palette B0 Set the umber of Gradation Palette B0 Set the umber of Gradation Palette B1 Set the umber of Gradation Palette B1 Set the umber of Gradation Palette B2 Set the umber of Gradation Palette B2 Set the umber of Gradation Palette B3 Set the umber of Gradation Palette B3 Set the umber of Gradation Palette B4 Set the umber of Gradation Palette B4 Set the umber of Gradation Palette B5 Set the umber of Gradation Palette B5 TST0: for LS1 test,must set to "0" RE: set register bank number
0 PA73 PA72 PA71 PA70 1* * * PA74
0 PB03 PB02 PB01 PB00 1* * * PB04
0 PB13 PB12 PB11 PB10 1* * * PB14
0 PB23 PB22 PB21 PB20 1* * * PB24
0 PB33 PB32 PB31 PB30 1* * * PB34
0 PB43 PB42 PB41 PB40 1* * *
0 PB53 PB52 PB51 PB50 1* TS 1 T0 * *
Note: The "" mark means "don't care"
Parentheses [ ] shows address for control register.
lim re P
0 1 0 1 0/1 0/1 0/1 1 1 1
ry a in
PB44 PB54 RE0 RE2 RE1
* This specification is subject to be changed without notice.
50
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
Control Register Table (Bank 3)
Control Register Gradation palette B6 (Lower nibble) Gradation palette B6 (Upper nibble) Gradation palette B7 (Lower nibble) Gradation palette B7 (Upper nibble) Gradation palette C0 (Lower nibble) Gradation palette C0 (Upper nibble) Gradation palette C1 (Lower nibble) Gradation palette C1 (Upper nibble) Gradation palette C2 (Lower nibble) Gradation palette C2 (Upper nibble) Gradation palette C3 (Lower nibble) Gradation palette C3 (Upper nibble) Gradation palette C4 (Lower nibble) Gradation palette C4 (Upper nibble) Register Access Control [0H] [1H] [2H] [3H] [4H] [5H] [6H] [7H] [8H] [9H] [AH] [BH] [CH] [DH] [FH]
Pins (for 80-family) & Bank Address & Code CSB RS WRB ROB RE2 RE1 RE0 D7 D6 D5 D4 D3 D2 D1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0
D0
Function
Note: The "" mark means "don't care"
Parentheses [ ] shows address for control register.
lim re P
0 1 0 1 0 1 1 1 1 0 0 1 0 1 0/1 0/1 0/1 1 1 1
Set the umber of 0 PB63 PB62 PB61 PB60 Gradation Palette B6 Set the umber of 1* * * PB64 Gradation Palette B6 Set the umber of 0 PB73 PB72 PB71 PB70 Gradation Palette B7 Set the umber of 1* * * PB74 Gradation Palette B7 Set the umber of 0 PC03 PC02 PC01 PC00 Gradation Palette C0 Set the umber of 1* * * PC04 Gradation Palette C0 Set the umber of 0 PC13 PC12 PC11 PC10 Gradation Palette C1 Set the umber of 1* * * PC14 Gradation Palette C1 Set the umber of 0 PC23 PC22 PC21 PC20 Gradation Palette C2 Set the umber of 1* * * PC24 Gradation Palette C2 Set the umber of 0 PC33 PC32 PC31 PC30 Gradation Palette C3 Set the umber of 1* * * PC34 Gradation Palette C3 Set the umber of 0 PC43 PC42 PC41 PC40 Gradation Palette C4 Set the umber of 1* * * PC44 Gradation Palette C4 TS TST0: for LS1 test,must set to "0" 1 T0 RE2 RE1 RE0 RE: set register bank number
ry a in
* This specification is subject to be changed without notice.
51
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
Control Register Table (Bank 4)
Control Register Gradation palette C5 (Lower nibble) Gradation palette C5 (Upper nibble) Gradation palette C6 (Lower nibble) Gradation palette C6 (Upper nibble) Gradation palette C7 (Lower nibble) Gradation palette C7 (Upper nibble) Display start common Static Pictgraph Control [7H] Display Select Control [8H] RAM Data length Set [9H] Electronic Volume (Lower nibble) Electronic Volume (Upper nibble) Register read Control Select Rf Extended power control [AH] [BH] [CH] [DH] 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 1 1 0 0 0 1 0 1 1 0 0 1 0 0 0 1 0 1 1 0 0 0 1 1 [0H] [1H] [2H] [3H] [4H] [5H] [6H] Pins (for 80-family) & Bank Address & Code D2 D1 D0 CSB RS WRB ROB RE2 RE1 RE0 D7 D6 D5 D4 D3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 1 1 0 0 1 Function
[EH] Register Access Control [FH]
Note: The "" mark means "don't care"
Parentheses [ ] shows address for control register.
lim re P
0 0 1 1 0 0 1 1 1 0 0 1 1 1 0/1 0/1 0/1 1 1 1
Set the umber of 0 PC53 PC52 PC51 PC50 Gradation Palette C5 Set the umber of 1* * * PC54 Gradation Palette C5 Set the umber of 0 PC63 PC62 PC61 PC60 Gradation Palette C6 Set the umber of 1* * * PC64 Gradation Palette C6 Set the umber of 0 PC73 PC72 PC71 PC70 Gradation Palette C7 Set the umber of 1* * * PC74 Gradation Palette C7 Set Common Driver 0* SC2 SC1 SC0 Start Line Set Static Pictgraph 1* * SPC1 SPC0 Drive Mode Select Plane(access/display) 0 PWM GLSB PSEL DSEL Set GLSB Bit. Select PWM Mode Set Data length on RAM Access 1* * * WLS 8-bit access or 16-bit access Set Electronic Vollume 0 DV3 DV2 DV1 DV0 Register (lower code) Set Electronic Vollume 1* DV6 DV5 DV4 Register (upper code) Set Register Address for read 0 RA3 RA2 RA1 RA0 Select Rf ratio of OSC circuit 1* RF2 RF1 RF0 DIS:Discharge capacitance of V0,V1,V2,V3,V4 Pins HPM : high power mode set 0 BF1 BF0 HPM DIS BF: Set Booster frequency TS TST0: for LS1 test,must set to "0" 1 T0 RE2 RE1 RE0 RE: set register bank number
ry a in
* This specification is subject to be changed without notice.
52
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
8.2 Functions of Control Registers
The EM65567 has many control registers. In case of control register access, upper nibble of data bus (D7~D4) represent register address, lower nibble of data bus (D3~D0) represent data. The access example is shown in the following. The Pins (CSB, RS, RDB, WRB) setting are for 80-family MPU interface. Only the setting of terminal (RDB,WRB) is different, when it is accessed by the 68-fanily MPU. (Example) X Address
D7 0 D6 0 D5 0 D4 0 D3 D2 D1 D0 AX3 AX2 AX1 AX0 Data CSB 0 RS 1 RDB WRB 1 0 RE2 0 RE1 0 RE0 0
Register address
Pins setting
Register Bank
In the writing to the control register, it is used directly as addressing D7~D4 of the data bus. In case of register read, first set RA register for specific register address, next can read specific register. Therefore, it is need 2-step for register read. Then, specific register output to D3~D0 of data bus. Except D3~D0 of data bus are all "H". Prohibit access to undefined register address area. When RS is "L", all read/write operations are accessed to display RAM. Then data bus doesn't include register address. In case of write, D3~D0 data is written to the register designated at D7~D4 in rising edge of the WRB signal. In case of read, register can output to data bus is RDB active period. Control register and display RAM are the equal access timing.
8.2.1 Data Write to Display RAM
D7 D6
D5 D4 D3 D2 Display RAM write data
The Display RAM data of 8-bit are written in the designated X and Y address. 8.2.2 Data Read from Display RAM
D7 D6
lim re P
D1 D0 CSB 0 RS 0 D1 D0 CSB 0 RS 0 D4 D3 D2 D1 D0 Internal Register read data CSB 0 RS 1
ry a in
RDB WRB RE2 1 0 0/1 RE1 0/1 RE0 0/1 RDB WRB RE2 0 1 0/1 RE1 0/1 RE0 0/1
D5 D4 D3 D2 Display RAM read data
The 8-bit contents of Display RAM designated in X. and Y address and read out. Immediately after data are set in X and Y address, dummy read is necessary one time. 8.2.3 Internal Register Data Read
D7 D6 D5 RDB WRB RE2 0 1 0/1 RE1 0/1 RE0 0/1
Mark shows "Don't care" This command is used to read data from an internal register. Before executing the command. You need to set the address and RE flag for reading data from the internal register. 8.2.4 X Address Register Set
D7 0 D6 0 D5 0 D4 0 D3 AX3 D2 AX2 D1 AX1 D0 AX0 CSB 0 RS 1 RDB WRB RE2 1 0 0 RE1 0 RE0 0
* This specification is subject to be changed without notice.
53
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(At the time of reset: {AX3, AX2, AX1, AX0}= 0H, read address: 0H)
D7 0 D6 0 D5 0 D4 1 D3 D2 AX6 D1 AX5 D0 AX4 CSB 0 RS 1 RDB WRB RE2 1 0 0 RE1 0 RE0 0
(At the time of reset: {AX6, AX5, AX4}= 0H, read address: 1H) Mark shows "Don't care" The AX register set to X-direction address of display RAM. In data setting, lower place and upper place are divided with 4-bit and 3-bit respectively. Be sure to do setting from the lower bit. 8.2.5 Y Address Register Set
D7 D6 D5 D4 D3 D2 D1 D0
0
0
1
0
AY3 AY2 AY1 AY0
CSB 0
RS 1
RDB WRB RE2 1 0 0
RE1 0
RE0 0
(At the tine of reset: {AY3, AY2, AY1, AY0}=0H, read address: 2H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS
0
0
1
0
AY6 AY5 AY4
0
1
(At the time of reset: {AY6, AY5, AY4}=0H, read address: 3H) Mark shows "Don't care"
The AY register set to Y-direction address of display RAM. In data setting, lower place and upper place are divided with 4-bit and 3-bit respectively. 00H to 41H are applicable to the values for AY6 to AY0, and 42H to FFH are not permitted. The address for (AY6 to AY0) = 40H, 41H are in the display RAM area for icon display.
8.2.6 Display Start Address Register Set
D7 D6 D5 D4 D3
0
1
0
lim re P
D2 D1 D0 CSB RS
ry a in
RDB WRB RE2 RE1 RE0
1
0
0
0
0
RDB WRB RE2
RE1
RE0
0
LA3
LA2
LA1 LA0
0
1
1
0
0
0
0
(At the tine of reset: {LA3, LA2, LA1, LA0}=0H, read address: 4H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
1
0
1
LA5 LA4
0
1
1
0
0
0
0
(At the time of reset: {LA5, LA4}=0H, read address: 5H) Mark shows "Don't care" This display line address is require to designate, and the designated address becomes the display line of COM0. The display of LCD panel is indicated in the increment direction of the designated display starting address to the line address.
LA5 0 0 1
LA4 0 0 1
LA3 0 0 1
LA2 0 0 1
LA1 0 0 1
LA0 0 1 1
Line Address 0 1 63
* This specification is subject to be changed without notice.
54
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
8.2.7 n Line Alternated Register Set
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
1
1
0
N3
N2
N1
N0
0
1
1
0
0
0
0
(At the tine of reset: {N3, N2, N1, N0}=0H, read address: 6H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
1
1
1
N5
N4
0
1
1
0
0
0
0
(At the time of reset: { N5, N4}=0H, read address: 7H) Mark shows "Don't care" The reverse line number of LCD alternated drive is required to set in the register. The line number has a limit, must keeps between from 2 to 64 lines. The values set up by the alternated register become enable when NLIN control bit is "1". When NLIN control bit is "0", alternated drive waveform reverses by each frame is generated.
N5 0 0
N4 0 0
1
1
Alternated Timing
(i) NLIN="0" (in case of 1/66 DUTY Display)
1st Line 2nd Line
LP
lim re P
1 1 1
3rd Line
nth line Cycle 1st Line 2nd Line 3rd Line
N3 0 0 1
N2 0 0
N1 0 0
N0 0 1
Line Address 2
ry a in
64
65st Line 66th Line 1st Line
FLM
M
(ii) NLIN="1"
nth Line
1st Line
2nd Line
LP
M
* This specification is subject to be changed without notice.
55
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
8.2.8 Display Control (1) Register Set
D7 D6 D5 D4
1
0
0
0
SHIF ALL ON/ T MON ON OFF
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
0
1
1
0
0
0
0
(At the tine of reset: {SHIFT, MON, ALLON, ON/OFF}=0H, read address: 8H) Various control of display is set up. ON/OFF To control ON/OFF of display ON/OFF = "0": Display OFF ON/OFF = "1": Display ON ALLON Regardless of the data for display, all is on. This control has priority over display normal/reverse commands. ALLON = "0": Normal display ALLON = "1": All display lighted MON
Select Monochrome or Gradation display MON = "0": Gradation display mode SHIFT MON = "1": Monochrome display mode
The shift direction of display scanning data in the common driver output is selected. SHIFT = "0": COM0 COM63 shift-scan SHIFT = "1": COM63 COM0 shift-scan
lim re P
ry a in
* This specification is subject to be changed without notice.
56
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
8.2.9 Display Control (2) Register
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
0
0
1
REV NLIN SWA REF
0
1
1
0
0
0
0
(At the tine of reset: {REV, NLIN, SWAP, REF}=0H, read address: 9H) Various control of display is set up. REF When MPU accesses to display RAM, the X address and data can reverse. The REF function shows in the table below: The order of segment driver output can be reversed by register by register setting, lessening the limitation in placing IC when assembling a LCD module.
REF 0
1
Access from MPU X Address D7-D0 D0(LSB) NH D7(MSB) D0(LSB) NH D7(MSB)
Note: maxH: The maximum X-address in each access mode. SWAP
When data to display RAM are written, the write data exchange bit order. SWAP = "0": Normal mode. In data writing, the data either of D7 to D0 or D15 to D0can be written to the display RAM. SWAP = "1": SWAP mode ON. In data writing the swapped data either of D7 to D0 or of D15 to D0 can be written to display RAM. Example of exchange bit order
lim re P
Internal Access X Address D7-D0 (LSB) NH (MSB) (MSB) maxH-NH (LSB)
Corresponding Segment Output SEG(8*NH)Output SEG(8*NH+7)Output SEG(8*(maxH-NH)+7)Output SEG(8*(maxH-NH))Output
ry a in
Write Data
SWAP = "0" SWAP = "1" D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0
Internal Data d7 d6 d5 d4 d3 d2 d1 d0 d0 d1 d2 d3 d4 d5 d6 d7
CAUTION: REF and SWAP both set to "1" When data write to display RAM, the write data is normal bit order. When data read from display RAM, the read data is exchanged bit order. NLIN The NLIN control n-line alternated drive. NLIN = "0": n-line alternated drive OFF. In each frame, the alternated signals (M) are reversed. NLIN ="1": n-line alternated drive ON. According to data set up in n-line alternated register, the alternation is made. * This specification is subject to be changed without notice. 57 2003/1/9 (V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
REV Corresponding to the data of display RAM, the lighting or not-lighting of the display is set up. REV ="0": When RAM data at "H", LCD at ON voltage (normal) REV ="1": When RAM data at "L", LCD at ON voltage (reverse) 8.2.10 Increment Control Register Set
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
0
1
0
AIM
AYI
AXI
0
1
1
0
0
0
0
Mark shows "Don't care" (At the tine of reset: {AIM, AYI, AXI}=0H, read address: AH) The increment mode is set up when accessing to display RAM. By AIM, AYI, AXI register, the setting up of increment operation/non-operation for the X address counter and the Y address counter every write access or every read access to display RAM is possible. In setting to this control register, the increment operation of address can be made without setting successive address for writing data or for reading data to display RAM from MPU. After the increment control register has been set. be sure to assign address to the X and Y address registers starting from the lowest bit. Because it is not assuring the data of X and Y address register after setting increment control register. The increment control of X and Y address by AIM, AYI, AXI registers is as follows. AIM 0 1 Address Increment Timing When writing to Display RAM or reading from Display RAM This is effective when access to successive address area Only when writing to Display RAM This is effective the case of "Read Modify Write AXI 0 1 0 1 Select Address Increment Operation Address is not increment X-Address is increment Y-Address is increment X and Y both are increment
lim re P
01H ....... max max
ry a in
Remark (1) (2) (3) (4)
AYI 0 0 1 1
(1) Regardless of AIM, no increment for AX and AY register. (2) According to the setting-up of AIM, automatically change X address. In accordance with the REF register, AX register and X address becomes as follows.
REF 0
Transition of AX Register
Transition of X Address Same as AX register
00H
1
maxH
.....
00H
Note: maxH: The internal maximum X-address in each access mode. (3) According to the setting-up of AIM, automatically change Y address. Regardless of REF, increment by loop of
* This specification is subject to be changed without notice.
58
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
Transition of AY Register
Transition of Y Address Same as AY register
00H
01H
.......
41H
(4) According to the setting-up of AIM, cooperative change X and Y address. When the X address exceed maxH, Y address increment occurs.
REF 0
Transition of AX and AY Register
AX: 00H 00H max AY: When each AX exceed maxH, increment AY 00H 00H 41H
Transition of X and Y Address Same as AX and AY register
AX: max AY: maxH 00H
1
Same as AY register
Note: maxH: The internal maximum X-address in each access mode.
In each operation mode, the following increment operation is performed: (i) (ii) (iii)
When gradation display mode and 8-bit access are selected: Address are incremented as described above. When gradation display mode and 16-bit access are selected: Two bytes are accessed by accessing the RAM once. The X-addresses increment in the order of 00H,01H,...2EH,and 2FH. When monochrome display mode and 8-bit access are selected:
In the monochrome display mode, 0H to 23H are available for X-addresses in the access area. PSEL = "0": The plane 0 area is selected, and the X-address change in increments in the order of 00H,01H,...22H, and 23H. and 23H. (iv) PSEL = "1": The plane 1 area is selected, and the X-address change in increments in the order of 00H,01H,...22H, When monochrome display mode and 16-biit access are selected: Two bytes are accessed by accessing the RAM once. PSEL = "0": The plane 0 area is selected, and the X-address change in increments in the order of 00H,01H,...10H,and 11H. PSEL = "1": The plane 1 area is selected, and the X-address change in increments in the order of 00H,01H,...10H,and 11H. 8.2.11 Power Control Register
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
lim re P
1 AMP HAL DCO ACL ON T N 0 1
ry a in
1
0
1
1
0
0
0
0
(At the tine of reset: {AMPON, HALT, DCON, ACL}=0H, read address: BH)
* This specification is subject to be changed without notice.
59
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
ACL The internal circuit can be initialized. This register is effective only at Master operation mode. ACL = "0": Normal operation ACL = "1": Initialization ON When the reset operation begins internally after ACL register sets to "1", the ACL register is automatically cleared to "0". The internal reset signal has been generated with a clock (built-in oscillation circuit or CK input) for the display. Therefore, install the WAIT period for the display clock two cycles at least. After WAIT period, next operation can handle. Since built-in oscillation circuit and external CK input can not be used in the slave mode, the setting of the ACL register becomes the invalidity. Certainly use the RESB terminal, when the reset is applied on the slave chip.
DCON The internal booster circuit is set ON/OFF DCON = "0": Booster circuit OFF DCON="1": Booster circuit ON HALT
The conditions of power saving are set ON/OFF by this command. HALT = "0": Normal operation HALT="1": Power-saving operation
When setting in the power-saving state, the consumed current can be reduced to a value near to the standby current. The internal condition at power saving are as follows. (a) (b) (c) (d) (e)
lim re P
ry a in
The oscillating circuit and power supply circuit are stopped. The LCD drive is stopped, and output of the segment driver and common driver are VSS level. The clock input from CK pin is inhibited. The contents of Display RAM data are maintained. The operational mode maintains the state of command execution before executing power saving command.
AMPON Command The internal OP-AMP circuit block (voltage regulator, electronic volume, and voltage conversion circuit) is set ON/OFF by
this command.
AMPON = "0": The internal OP-AMP circuit OFF AMPON = "1": The internal OP-AMP circuit ON
* This specification is subject to be changed without notice.
60
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
8.2.12 LCD Duty Set
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
1
0
0
DS2
DS1
DS0
0
1
1
0
0
0
0
(At the time of reset: {DS2, DS1, DS0}=0H, read address: CH) Mark shows "Don't care" The DS register set to LCD display duty. DS2 0 0 0 0 1 1 1 1 DS1 0 0 1 1 0 0 1 1 DS0 0 1 0 1 0 1 0 1 Display width and Duty 8-dot width display in Y-direction, 1/10 duty 16-dot width display in Y-direction, 1/18 duty 24-dot width display in Y-direction, 1/26 duty 32-dot width display in Y-direction, 1/34 duty 40-dot width display in Y-direction, 1/42 duty 48-dot width display in Y-direction, 1/50 duty 56-dot width display in Y-direction, 1/58 duty 64-dot width display in Y-direction, 1/66 duty
Partial display can be made possible by setting an arbitrary duty ratio. 8.2.13 Booster Set
D7 D6 D5
1
1
0
(At the time of reset: {VU2, VU1, VU0}=0H, read address: DH) Mark shows "Don't care" VU1 0 0 1 1 VU0 0 1 0 1 The booster steps set to VU register
Booster Operation Booster disable (No operation) 2 times voltage output 3 times voltage output 4 times voltage output
lim re P
D4 D3 D2 D1 D0 CSB
RS
1
VU1
VU0
0
1
ry a in
RDB WRB RE2 RE1 RE0
1
0
0
0
0
8.2.14 Bias Setting Register Set
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
1
1
0
B2
B1
B0
0
1
1
0
0
0
0
(At the time of reset: {B2, B1, B0}=0H, read address: EH) Mark shows "Don't care" This register is used to set a bias ratio. A bias ratio can be selected from 1/9, 1/8, 1/7, 1/6, and 1/5 by setting B2, B1, and B0. B2 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 Bias 1/9 Bias 1/8 Bias 1/7 Bias 1/6 Bias 1/5 Bias Prohibit code Prohibit code Prohibit code 61 2003/1/9 (V0.1)
* This specification is subject to be changed without notice.
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
8.2.15 Register Access Control
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
1
1
1
TST0 RE2
RE1
RE0
0
1
1
0
0/1
0/1
0/1
(At the time of reset: {TST0, RE2, RE1, RE0}=0H, read address: FH) Mark shows "Don't care" The RE register set to number of register bank. Access to each control register, set RE register at first. The TST0 register use for test of LSI, Therefore this register must be set to "0" 8.2.16 Gradation Palette Register (PA0~PA7, PB0~PB7, PC0~PC7)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
0
0
0
PA03 PA02 PA01 PA00
0
1
1
0
(Read address: 0H)
D7 D6 D5 D4 D3 D2 D1
0
0
0
1
(Read address: 1H) (At the time of reset: PA04~PA00 = "00000") Mark shows "Don't care"
D7
D6
D5
0
0
1
(Read address: 2H)
D7 D6 D5
0
0
1
re P
D4 D3 D2 D1
0
PA13 PA12 PA11 PA10
in lim
PA04 0 1 1 0
D0 CSB RS
D0
CSB
RS
RDB WRB RE2
ry a
RE1 RE0
0
0
1
0
0
1
RDB WRB RE2
RE1
RE0
0
1
1
0
0
0
1
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
1
PA14
0
1
1
0
0
0
1
(Read address: 3H) (At the time of reset: PA14~PA10 = "00101") Mark shows "Don't care"
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
0
1
0
0
PA23 PA22 PA21 PA20
0
1
1
0
0
0
1
(Read address: 4H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
1
0
1
PA24
0
1
1
0
0
0
1
(Read address: 5H) (At the time of reset: PA24~PA20 = "01010") Mark shows "Don't care"
* This specification is subject to be changed without notice.
62
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
0
1
1
0
PA33 PA32 PA31 PA30
0
1
1
0
0
0
1
(Read address: 6H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
1
1
1
PA34
0
1
1
0
0
0
1
(Read address: 7H) (At the time of reset: PA34~PA30 = "01110") Mark shows "Don't care"
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
1
0
0
0
PA43 PA42 PA41 PA40
0
1
(Read address: 8H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS
1
0
0
(Read address: 9H)
(At the time of reset: PA44~PA40 = "10001") Mark shows "Don't care"
D7
D6
D5
1
0
1
(Read address: AH)
D7 D6 D5
lim re P
D4 D3 D2 D1 D0 CSB RS
1
PA44
0
1
ry a in
1 0 0 0 1
RDB WRB RE2 RE1 RE0
RDB WRB RE2
RE1
RE0
1
0
0
0
1
RDB WRB RE2
RE1
RE0
0
PA53 PA52 PA51 PA50
0
1
1
0
0
0
1
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
1
0
1
1
PA54
0
1
1
0
0
0
1
(Read address: BH) (At the time of reset: PA54~PA50 = "10101") Mark shows "Don't care"
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
1
1
0
0
PA63 PA62 PA61 PA60
0
1
1
0
0
0
1
(Read address: CH)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
1
0
1
PA64
0
1
1
0
0
0
1
(Read address: DH) (At the time of reset: PA64~PA60 = "11010") Mark shows "Don't care"
* This specification is subject to be changed without notice.
63
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
0
0
0
0
PA73 PA72 PA71 PA70
0
1
1
0
0
1
0
(Read address: 0H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
0
0
1
PA74
0
1
1
0
0
1
0
(Read address: 1H) (At the time of reset: PA74~PA70 = "11111") Mark shows "Don't care"
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
0
0
1
0
PB03 PB02 PB01 PB00
0
1
(Read address: 2H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS
0
0
1
(Read address: 3H)
(At the time of reset: PB04~PB00 = "00000") Mark shows "Don't care"
D7
D6
D5
0
1
0
(Read address: 4H)
D7 D6 D5
lim re P
D4 D3 D2 D1 D0 CSB RS
1
PB04
0
1
ry a in
1 0 0 1 0
RDB WRB RE2 RE1 RE0
RDB WRB RE2
RE1
RE0
1
0
0
1
0
RDB WRB RE2
RE1
RE0
0
PB13 PB12 PB11 PB10
0
1
1
0
0
1
0
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
0
1
0
1
PB14
0
1
1
0
0
1
0
(Read address: 5H) (At the time of reset: PB14~PB10 = "00101") Mark shows "Don't care"
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
0
1
1
0
PB23 PB22 PB21 PB20
0
1
1
0
0
1
0
(Read address: 6H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
1
1
1
PB24
0
1
1
0
0
1
0
(Read address: 7H) (At the time of reset: PB24~PB20 = "01010") Mark shows "Don't care"
* This specification is subject to be changed without notice.
64
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
1
0
0
0
PB33 PB32 PB31 PB30
0
1
1
0
0
1
0
(Read address: 8H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
0
0
1
PB34
0
1
1
0
0
1
0
(Read address: 9H) (At the time of reset: PB34~PB30 = "01110") Mark shows "Don't care"
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
1
0
1
0
PB43 PB42 PB41 PB40
0
1
(Read address: AH)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS
1
0
1
(Read address: BH)
(At the time of reset: PB44~PB40 = "10001") Mark shows "Don't care"
D7
D6
D5
1
1
0
(Read address: CH)
D7 D6 D5
lim re P
D4 D3 D2 D1 D0 CSB RS
1
PB44
0
1
ry a in
1 0 0 1 0
RDB WRB RE2 RE1 RE0
RDB WRB RE2
RE1
RE0
1
0
0
1
0
RDB WRB RE2
RE1
RE0
0
PB53 PB52 PB51 PB50
0
1
1
0
0
1
0
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
1
1
0
1
PB54
0
1
1
0
0
1
0
(Read address: DH) (At the time of reset: PB54~PB50 = "00101") Mark shows "Don't care"
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
0
0
0
0
PB63 PB62 PB61 PB60
0
1
1
0
0
1
1
(Read address: 0H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
0
0
1
PB64
0
1
1
0
0
1
1
(Read address: 1H) (At the time of reset: PB64~PB60 = "11010") Mark shows "Don't care"
* This specification is subject to be changed without notice.
65
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
0
0
1
0
PB73 PB72 PB71 PB70
0
1
1
0
0
1
1
(Read address: 2H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
1
0
1
PB74
0
1
1
0
0
1
1
(Read address: 3H) (At the time of reset: PB74~PB70 = "11111") Mark shows "Don't care"
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
0
1
0
0
PC03 PC02 PC01 PC00
0
1
(Read address: 4H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS
0
1
0
(Read address: 5H)
(At the time of reset: PC04~PC00 = "00000") Mark shows "Don't care"
D7
D6
D5
0
1
1
(Read address: 6H)
D7 D6 D5
lim re P
D4 D3 D2 D1 D0 CSB RS
1
PC04
0
1
ry a in
1 0 0 1 1
RDB WRB RE2 RE1 RE0
RDB WRB RE2
RE1
RE0
1
0
0
1
1
RDB WRB RE2
RE1
RE0
0
PC13 PC12 PC11 PC10
0
1
1
0
0
1
1
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
0
1
1
1
PC14
0
1
1
0
0
1
1
(Read address: 7H) (At the time of reset: PC14~PC10 = "00101") Mark shows "Don't care"
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
1
0
0
0
PC23 PC22 PC21 PC20
0
1
1
0
0
1
1
(Read address: 8H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
0
0
1
PC24
0
1
1
0
0
1
1
(Read address: 9H) (At the time of reset: PC24~PC20 = "01010") Mark shows "Don't care"
* This specification is subject to be changed without notice.
66
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
1
0
1
0
PC33 PC32 PC31 PC30
0
1
1
0
0
1
1
(Read address: AH)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
0
1
1
PC34
0
1
1
0
0
1
1
(Read address: BH) (At the time of reset: PC34~PC30 = "01110") Mark shows "Don't care"
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
1
1
0
0
PC43 PC42 PC41 PC40
0
1
(Read address: CH)
D7 D6 D5
1
1
0
(Read address: DH)
(At the time of reset: PC44~PC40 = "10001") Mark shows "Don't care"
D7
D6
D5
0
0
0
(Read address: 0H)
D7 D6 D5
lim re P
D4 D3 D2 D1 D0 CSB RS
1
PC44
0
1
ry a in
RDB WRB RE2 RE1 RE0
1
0
0
1
1
RDB WRB RE2
RE1
RE0
1
0
0
1
1
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
0
PC53 PC52 PC51 PC50
0
1
1
0
1
0
0
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
0
0
0
1
PC54
0
1
1
0
1
0
0
(Read address: 1H) (At the time of reset: PC54~PC50 = "10101") Mark shows "Don't care"
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
0
0
1
0
PC63 PC62 PC61 PC60
0
1
1
0
1
0
0
(Read address: 2H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
0
1
1
PC64
0
1
1
0
1
0
0
(Read address: 3H) (At the time of reset: PC64~PC60 = "11010") Mark shows "Don't care" * This specification is subject to be changed without notice. 67 2003/1/9 (V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
D7
D6
D5
D4
D3
D2
D1
D0
CSB
RS
RDB WRB RE2
RE1
RE0
0
1
0
0
PC73 PC72 PC71 PC70
0
1
1
0
1
0
0
(Read address: 4H)
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
1
0
1
PC74
0
1
1
0
1
0
0
(Read address: 5H) (At the time of reset: PC74~PC70 = "11111") Mark shows "Don't care" These gradation palette register set up gradation level. The EM65567 has 32 gradation levels. Gradation level table [Three groups of palettes Aj,Bj, and Cj (j=0-7) are available]
Palette 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Gradation level
Remarks
gradation palette 0 initial value
Palette 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Gradation level
0 1/31 2/31 3/31 4/31 5/31 6/31 7/31 8/31 9/31 10/31 11/31 12/31 13/31 14/31 15/31
lim re P
gradation palette 1 initial value gradation palette 2 initial value gradation palette 3 initial value
16/31 17/31 18/31 19/31 20/31 21/31 22/31 23/31 24/31 25/31 26/31 27/31 28/31 29/31 30/31 31/31
ry a in
Remarks
gradation palette 4 initial value gradation palette 5 initial value gradation palette 6 initial value gradation palette 7 initial value
* This specification is subject to be changed without notice.
68
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
8.2.17 Display Start Common Set
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
0
1
1
0
SC2
SC1
SC0
0
1
1
0
1
0
0
(At the time of reset:{ SC2,SC1,SC0}=0H, read address: 6H) Mark shows "Don't care" The SC register set up the scanning start output of the common driver. SC2 0 0 0 0 1 1 1 1 SC1 0 0 1 1 0 0 1 1 SC0 0 1 0 1 0 1 0 1 Display starting common when SHIFT=0 COM0~ COM8~ COM16~ COM24~ COM32~ COM40~ COM48 COM56 COM63 shift-scan COM0 shift-scan Display starting common when SHIFT=1 COM63~ COM55~ COM47~ COM39~ COM31~ COM23~ COM15~ COM7~
SHIFT="0": COM0
SHIFT="1": COM63
8.2.18 Static Pictograph Control
D7 D6 D5 D4
0
1
1
(At the time of reset:{ SPC1,SPC0}=0H, read address: 7H) Mark shows "Don't care"
This command is used to select a signal to drive static pictograph.
lim re P
D3 D2 D1 D0 CSB RS
ry a in
RDB WRB RE2 RE1 RE0
1
SPC1 SPC0
0
1
1
0
1
0
0
SPC1 SPC0 Signal for static pictograph 0 0 VSS level is always output at SCOM and SSEG 0 1 Phase deviates by 45 degrees at SCOM and SSEG 1 0 Phase deviates by 90 degrees at SCOM and SSEG 1 1 Phase deviates by 135 degrees at SCOM and SSEG Drive waveform when (SPC1, SPC0) =(0, 1)
VDD level SCOM VDD level SSEG VSS level VSS level
1 frame
1 frame
Drive waveform when (SPC1, SPC0) =(1, 0)
* This specification is subject to be changed without notice.
69
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
VDD level SCOM VDD level SSEG VSS level VSS level
1 frame
1 frame
Drive waveform when (SPC1, SPC0) =(1, 1)
VDD level SCOM VSS level VDD level SSEG VSS level
1 frame
1 frame
8.2.19 Display Select Control
D7 D6 D5 D4
1
0
0
(At the time of reset: {PWM, GLSA, PSEL, DSEL} = 0H, read address: 8H) PSEL
The PSEL register select assessable plane from MPU in the monochrome display mode (MON="1"). PSEL = "0": The plane 0 can access PSEL = "1": The plane 1 can access DSEL command The DSEL register select active plane for display in the monochrome display mode(MON="1"). DSEL = "0": The plane 0 is active for display. DSEL = "1": The plane 1 is active for display. GLSB For the segment driver of 4-gradation display, select 4 gradations from 8 gradations using the 2 bits written to the corresponding RAM area and the 1 bit supplemented by the gradation LSB circuit. Supplement the 1 bit of data by setting the gradation LSB register (GLSB). Gradation LSB = "0": Selects 0 as the LSB information on the RAM for 4-gradation segment driver. Gradation LSB = "1": Selects 1 as the LSB information on the RAM for 4-gradation segment driver. PWM The PWM register selection the gradation display mode. * This specification is subject to be changed without notice. 70 2003/1/9 (V0.1)
lim re P
D3 D2 D1 D0 CSB RS
0
PWM GLS PSEL DSEL
0
1
ry a in
RDB WRB RE2 RE1 RE0
1
0
1
0
0
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
PWM = "0": Variable display mode using 8 gradations selected from 32 gradations PWM = "1": 8-gradation fixed display mode 8.2.20 RAM Data Length Set
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
0
0
1
WLS
0
1
1
0
1
0
0
(At the time of reset: {WLS} = 0H, read address: 9H) Mark shows "Don't care" The WLS register select data bus size for access from MPU WLS = "0": The data bus size is 8-bits width WLS = "1": The data bus size is 16-bits width When MPU access to control register using 16-bits bus size, high byte data is ignored. 8.2.21 Electronic Volume Register Set
D7 D6 D5
1
0
1
(Read address: AH)
D7 D6 D5
1
0
1
(Read address: BH)
(At the time of reset: {DV6~DV0} = 00H) Mark shows "Don't care"
lim re P
D4 D3 D2 D1 D0 CSB RS
0
DV3 DV2 DV1 DV0
0
1
D4
D3
D2
D1
D0
CSB
RS
1
DV6 DV5 DV4
0
1
ry a in
RDB WRB RE2 RE1 RE0
1
0
1
0
0
RDB WRB RE2
RE1
RE0
1
0
1
0
0
The DV register can control V0 voltage. The DV register has 7-bits, so can select 128 level voltage. DV6 0 0 DV5 0 0 DV4 0 0 DV3 0 0 1 1 DV2 0 0 DV1 0 0 DV0 0 1 Output voltage Smaller Larger
1 1
1 1
1 1
1 1
1 1
0 1
The output voltage at VREG is specified by equation (1). VREG = VREF * N * 0.9-----------------------------------------------------------(1) (N: Number of boosting steps) The LCD driver voltage V0 is determined by VREG level and electronic volume code equation (2). V0 = 0.5 * VREG + M * (VREG - 0.5VREG) / 127 --------------------------(2) * This specification is subject to be changed without notice. 71 2003/1/9 (V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(M: DV6 to DV0 register values) In order to prevent transient voltage from generating when an electronic volume code is set, the circuit design is such that the set value is not reflected as a level immediately after only the upper bits (DV6-DV4) of the electronic code have been set. The set value becomes valid when the lower bits (DV3-DV0) of the electronic control volume code have also been set.
8.2.22 Internal Register Read Address
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
1
0
1
RA3 RA2
RA1
RA0
0
1
1
0
1
0
0
(At the time of reset: {RA3, RA2, RA1, RA0} = CH) The RA register set to specify the address for register read operation. The EM65567 has many registers and has register bank. Therefore, it is need 4-steps to read to read the specific register in maximum case. (1) (2) (3) (4) Write 04H to RE register for access to RA register. Writes specific register address to RA register. Write specific register bank to RE register. Read specific contents.
8.2.23 Resistance Ratio of CR Oscillator
D7 D6 D5 D4 D3 D2
1
1
0
(At the time of reset: {RF2, RF1, RF0} = 0H, read address: DH) Mark shows "Don't care"
lim re P
D1 D0 CSB RS
ry a in
RDB WRB RE2 RE1 RE0
1
RF2
RF1
RF0
0
1
1
0
1
0
0
The RF registers can control resistance ratio of CR oscillator. Therefore frame frequency can change RF registers setting. When change RF registers value, should be need to check LCD display quality. RF2 RF1 RF0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Operation Initial Resistance Ratio 0.8 times of initial Resistance Ratio 0.9 times of initial Resistance Ratio 1.1 times of initial Resistance Ratio 1.2 times of initial Resistance Ratio Prohibit Code Prohibit Code Prohibit Code
* This specification is subject to be changed without notice.
72
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
8.2.24 Extended power control
D7 D6 D5 D4 D3 D2 D1 D0 CSB RS RDB WRB RE2 RE1 RE0
1
1
1
0
HPM
DIS
0
1
1
0
1
0
0
At the time of reset: {HPM, DIS} = 0H, {BF1,BF0}=0H;read address: EH) mark shows "Don't care"
The DIS register can control capacitors discharged that connected between the power supply V1-V4 for LCD drive voltage and VSS. Caution: V0 is discharged to VDD.
DIS = "0": Discharge OFF DIS = "1": Discharge start The HPM register is the power control for the power supply circuit for liquid crystal drive. HPM = "H": High power mode HPM = "L": Normal mode
BF1~BF0: The operating frequency in the booster is selected. When the boosting frequency is high, the driving ability of booster become high, but the current consumption is increased. Adjust the boosting frequency considering the external capacitors and the current consumption. BF1 0 0 1 1 BF0 0 1 0 1
lim re P
Operating clock frequency in the booster 1.5K Hz * 8 1.5K Hz * 4 1.5K Hz * 2 1.5 K Hz
ry a in
* This specification is subject to be changed without notice.
73
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
9.
Relationship between Setting and Common/Display RAM
The relationship between the COM pin numbers and the addresses in the Y-direction on the display RAM changes according to the SHIFT command. LCD Duty Set command. Display Starting Common Position Set command, and Display Starting Line Set command. When "0" is selected for the display starting line: The relationship between the COM pin and the addresses in the vertical direction of the display RAM (hereafter called MY) changes on an 8-dots basis according to the LCD Duty Set command and the Display Starting Common Position Set command. When the SHIFT bit is "0", the common position change in the forward direction. When "1" they change reverse direction. When "0" is selected as the values for LA5 to LA0 in the Display Starting Line Set command, the MY number corresponding to the display starting position is "0". The MY numbers are sequentially shifted backward when display occurs. In any case, the relations of COMA = MY64 and COMB = MY65 do not change. When non-zero is selected for the display starting line:
The relationship between the COM pins and the addresses in the vertical direction on the display RAM, MY changes on an 8dots basis according to the information in the LCD Duty Set command and Display Starting Common Position Set command. The common positions change in the forward when the SHIFT bit is "0", and change in the reverse direction when the SHIFT bit is "1". If non-zero is selected for the values for LA5 to LA0 by the Display Starting Line set command. the MY number corresponding to the display starting position shifts by the set value. The MY number shifts backward when display occurs. If it exceeds 63, it returns to 0, and the shifts sequentially. In any case, the relations of COMA = MY64 and COMB = MY65 do not change.
lim re P
ry a in
* This specification is subject to be changed without notice.
74
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
10. Absolute maximum ratings 10.1 Absolute maximum ratings
Item Symbol Condition Pin use Rating Unit Supply voltage (1) VDD VDD -0.3 ~ + 4.0 V Supply voltage (2) VEE VEE -0.3 ~ + 4.0 V Supply voltage (3) VOUT VOUT --0.3 ~ + 13.0 V Supply voltage (4) VREG VREG -0.3 ~ + 13.0 V Ta=25 Supply voltage (5) V0 V0 -0.3 ~ + 13.0 V Supply voltage (6) V1,V2,V3,V4 V1,V2,V3,V4 -0.3 ~ V0+ 0.3 V Input voltage VI *1 -0.3 ~ VDD+ 0.3 V Storage -45 ~ +125 Tstg temperature 1: D0~D15, CSB, RS, M/S, M86, P/S, WRB, RDB, CK, CKS, LP, FLM, M, CLK, RESB, TEST, VREF Pins
10.2 Recommended operating conditions
Item Supply voltage Operating voltage Symbol VDD1 VEE V0 VOUT VREG VREF Topr Application Pin VDD VEE V0 VOUT VREG VREF Min. 1.8 2.4 5 2.4 -30 Max. 3.3 3.3 12 12 10.8 3.3 80
Operating temperature
1 shows applying voltage to VSS pin.
2 shows applying voltage to VSS pin. Usually, if applying voltage is same as VDD. Connect to VDD pin. 3 shows the voltage relationship of V0>V1>V2>V3>V4>VSS is required. 4 shows applying voltage to VSS pin.. In the case of using the voltage regulator. The voltage relationship of VREFVEE is required.
lim re P
ry a in
Unit V V V V V V Note *1 *2 *3 *4
* This specification is subject to be changed without notice.
75
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
11. DC characteristics
VSS=0V , VDD = 1.8~3.3V , Ta = -30 ~80 Item High level input voltage Low level input voltage High level output current Low level output current High level output current Low level output current Input leakage current Output leakage current LCD driver output resistance LCD driver output resistance Standby current through VDD pin Oscillator frequency (variable gradation mode) Oscillator frequency (8 gradation mode) Oscillator frequency (monochrome mode) Symbol VIH VIL IOH1 IOL1 IOH2 IOL2 ILI ILO RON RON ISTB fosc fosc VOH = VDD-0.4V VOL= 0.4V VOH = VDD-0.4V VOL= 0.4V VI = VSS or VDD VI = VSS or VDD |Von| = 0.5V V0=10V V0=6V Condition Min. 0.8VDD 0 -0.4 0.4 -0.1 0.1 -2 -2 1.0 1.2 1.5 Typ. 0.9VDD 0.1VDD -0.5 0.5 -0.2 0.2 0 Max. VDD 0.2VDD -0.6 0.6 -0.3 0.3 2 Unit V V mA mA mA mA A A K K A KHz KHz KHz V V V 55 130 30 65 70 160 40 80 A A A A V Pin used 1 1 2 2 3 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
|Von| = 0.5V, VDD=3V
VDD=3V, Ta=25 , Rf setting = (Rf2,Rf1,Rf0)=(00 0) VDD=3V , Ta=25, fosc Rf setting = (Rf2,Rf1,Rf0)=(000) Four times boosting VOUT1 RL = 500K (VOUT-VSS) Booster output Three times boosting voltage VOUT2 RL = 500K (VOUT-VSS) on VOUT pin Two times boosting VOUT3 RL = 500K(VOUT-VSS) VDD = 3V, 4 times booster IDD1 All ON pattern VDD = 3V, 4 times booster IDD2 Checker pattern Current consumption VDD = 3V, 3 times booster IDD2 All ON pattern VDD = 3V, 3 times booster IDD2 Checker pattern VEE =2.4V~3.3V, VREG output voltage VREG VREF=2.4~3.3, N times boosting (N=2 to 4)
re P
CK=0, CSB=VDD, Ta=25, VDD=3V
VDD=3V , Ta=25, Rf setting = (Rf2,Rf1,Rf0)=(000)
in lim
260 58 8 4*VEE *0.95 3*VEE *0.95 2*VEE *0.95
ry a
0 2 1.3 1.7 2 1.6 2.2 2.5 15 5 372 84 12 484 110 16
(VREF*N*0.9) VREF*N (VREF*N*0.9) *0.95 *0.9 *1.05
* This specification is subject to be changed without notice.
76
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
Relationship of oscillating frequency (fosc) and external clock frequency (fCK) to LCD frame frequency (fFLM) is each display mode Original Ratio of display duty cycle (1/D) Display mode oscillating clock 1/66, 1/58, 1/50 1/42, 1/34, 1/26 1/18 1/10 When use Variable fosc/(2*31*D) fosc/(4*31*D) fosc/(8*31*D) fosc/(16*31*D) built-in gradation oscillating Simple gradation fosc/(2*7*D) fosc/(4*7*D) fosc/(8*7*D) fosc/(16*7*D) circuit (fosc) Monochrome fosc/(2*1*D) fosc/(4*1*D) fosc/(8*1*D) fosc/(16*1*D) When use Variable fCK/(2*31*D) fCK /(4*31*D) fCK /(8*31*D) fCK /(16*31*D) external clock gradation from CK pin. Simple gradation fCK /(2*7*D) fCK /(4*7*D) fCK /(8*7*D) fCK /(16*7*D) (fCK) Monochrome fCK /(2*1*D) fCK /(4*1*D) fCK /(8*1*D) fCK /(16*1*D) Pin used: 2 D0~D15 pins 3 LP, FLM, M, CLK pins Pin used
FLM
1 D0-D15, CSB, RS, M/S, M86, RDB, WRB, CK, CKS, CLK, LP, FLM, M, P/S, RESB, TEST pins.
4 CSB, RS, M/S, M86, RDB, WRB, CK, CKS, P/S, RESB, TEST pins
5 Applied when D0~D15, CLK, LP, FLM, and M are in the state of high impedance.
6 SEGA0~SEGA95, SEGB0~SEGB95, SEGC0~SEGC95. COM0~COM63, COMA, COMB pins Resistance when being applied 0.5V between each output pin and each power supply (V0, V1, V2, V3, V4) and when being applied 1/9 bias. 7 SSEG, SCOM pins

8 VDD pin, VDD pin current without load at the stoppage of original oscillating clock and at non-select (CSB=VDD) 9 Oscillating frequency, when using the built-in oscillating circuit (variable gradation display mode)
10 Oscillating frequency, when using the built-in oscillating circuit (8 gradation fixed display mode) 11 Oscillating frequency, when using the built-in oscillating circuit (monochrome display mode) 12 VOUT pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 4 times is used, this pin is applied. VEE=2.4~3.3 V, The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/9, 1/66 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1" 13 VOUT pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 3 times is used, this pin is applied. VEE=2.4~3.3 V, The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/9, 1/66 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1" 14 VOUT pin. When using the built-in oscillating circuit, the built-in power supply is used, and boosting 2 times is used, this pin is applied. VEE=2.4~3.3 V, The electronic control is preset (The code is ("1 1 1 1 1 1 1")). Measuring conditions: bias=1/5~1/9, 1/66 duty, without load. RL=500 K (between VOUT and VSS), C1=C2=1.0F, C3=0.1F, DCON=AMPON="1" 15 VDD, VEE pin. When the built-in oscillating circuit and built-in power supply are used and there is no access from * This specification is subject to be changed without notice. 77 2003/1/9 (V0.1)
lim re P
ry a in
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
MPU. This pin is applied. Boosting 4 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display ALL ON pattern (on monochrome display mode) and LCD driver pin with no load. Measuring conditions: VDD=VEE=VREF, C1=C2=1.0F, C3=0.1F, DCON=AMPON="1" 16 VDD, VEE pin. When the built-in oscillating circuit and built-in power supply are used and there is no access from MPU. This pin is applied. Boosting 4 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display a checkered pattern (on monochrome display mode) and LCD driver pin with no load. Measuring conditions: VDD=VEE=VREF, C1=C2=1.0F, C3=0.1F, DCON=AMPON="1" 17 VDD, VEE pin. When the built-in oscillating circuit and built-in power supply are used and there is no access from MPU. This pin is applied. Boosting 3 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display ALL ON pattern (on monochrome display mode) and LCD driver pin with no load. Measuring conditions: VDD=VEE=VREF, C1=C2=1.0F, C3=0.1F, DCON=AMPON="1" 18 VDD, VEE pin. When the built-in oscillating circuit and built-in power supply are used and there is no access from MPU. This pin is applied. Boosting 3 times is used the electronic control is preset (The code is ("1 1 1 1 1 1 1")). Display a checkered pattern (on monochrome display mode) and LCD driver pin with no load. Measuring conditions: VDD=VEE=VREF, C1=C2=1.0F, C3=0.1F, DCON=AMPON="1" 19 VREG pin. Measuring conditions: VEE=VREF=2.4~3.3 V, bias=1/5~1/9, 1/66 duty.
lim re P
ry a in
* This specification is subject to be changed without notice.
78
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
12. AC characteristic
(1) 80-family MCU write timing
tAS8
tAH8
CSB RS
tW RLW 8 W RB tDS8 tW RHW 8 tDH8
D0-D15
VSS=0V, VDD = 2.7~3.3V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCWR8 tWRLW8 tWRHW8 tDS8 tDH8
lim re P
Condition Min. 0 0 250 60 185 60 5 Symbol tAH8 tAS8 tCYCWR8 tWRLW8 tWRHW8 tDS8 tDH8 Condition Min. 0 0 330 80 240 80 10 Symbol tAH8 tAS8 tCYCWR8 tWRLW8 tWRHW8 tDS8 tDH8 Condition Min. 0 0 660 140 500 100 20
ry a in
tCYCW R8
Typ.
Max.
Unit ns ns ns ns ns ns ns
Pin used CSB RS WRB (R/WB)
D0~D15
VSS=0V, VDD = 2.4~2.7V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS WRB (R/WB) D0~D15
VSS=0V, VDD = 2.4~3.3V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS WRB (R/WB) D0~D15
Note: All the timings must be specified relative to 20% and 80% of VDD voltage. * This specification is subject to be changed without notice. 79 2003/1/9 (V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(2) 80-family MCU read timing
tAS8 CSB RS
tAH8
RDB
tRDLW 8 tRDHW 8 tRDH8
tRDD8 D0-D15
VSS=0V , VDD = 2.7~3.3V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in read Read pulse "L" width Read pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCRD8 tRDLW8 tRDHW8 tRDD8 tRDH8
VSS=0V , VDD = 2.4~2.7V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in read Read pulse "L" width Read pulse "H" width Data setup time Data hold time Symbol tAH8 tAS8 tCYCRD8 tRDLW8 tRDHW8 tRDD8 tRDH8
lim re P
Condition Min. 0 0 450 200 185 10 CL = 80 pF Condition Min. 0 0 600 220 240 10 CL = 80 pF Symbol tAH8 tAS8 tCYCRD8 tRDLW8 tRDHW8 tRDD8 tRDH8 Condition Min. 0 0 1000 450 500 10
ry a in
tCYCRD8
Typ.
Max.
250
Unit ns ns ns ns ns ns ns
Pin used CSB RS RDB(E)
D0~D15
Typ.
Max.
350
Unit ns ns ns ns ns ns ns
Pin used CSB RS RDB(E) D0~D15
VSS=0V , VDD = 1.8~2.4V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in read Read pulse "L" width Read pulse "H" width Data setup time Data hold time Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS RDB(E) D0~D15
CL = 80 pF
650
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
* This specification is subject to be changed without notice.
80
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(3) 68-family MCU write timing
tAS6 CSB RS
tAH6
R/W B (W RB)
E (RDB)
tEHW 6
tELW 6
tDS6
D0-D15
VSS=0V , VDD = 2.7 ~3.3V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCWR6 tELW6 tEHW6 tDS6 tDH6
lim re P
Condition Min. 0 0 250 60 185 60 5 Symbol tAH6 tAS6 tCYCWR6 tELW6 tEHW6 tDS6 tDH6 Condition Min. 0 0 330 80 240 80 10 Symbol tAH6 tAS6 tCYCWR6 tELW6 tEHW6 tDS6 tDH6 Condition Min. 0 0 660 140 500 100 20
ry a in
tCYCW R6
tDH6
Typ.
Max.
Unit ns ns ns ns ns ns ns
Pin used CSB RS RDB(E)
D0~D15
VSS=0V , VDD = 2.4 ~2.7V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS RDB(E) D0~D15
VSS=0V , VDD = 1.8 ~2.4V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS RDB(E) D0~D15
Note: All the timings must be specified relative to 20% and 80% of VDD voltage. * This specification is subject to be changed without notice. 81 2003/1/9 (V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(4) 68-family MCU read timing
tAS6 CSB RS
tAH6
R/W B (W RB)
E (RDB)
tEHW 6
tELW 6
tRDD6
D0-D15
VSS=0V , VDD = 2.7~3.3V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Symbol tAH6 tAS6 tCYCRD6 tELW6 tEHW6 tRDD6 tRDH6
lim re P
Condition Min. 0 0 450 200 185 10 CL=80pF Symbol tAH6 tAS6 tCYCRD6 tELW6 tEHW6 tRDD6 tRDH6 Condition Min. 0 0 600 220 240 10 CL=80pF Symbol tAH6 tAS6 tCYCRD6 tELW6 tEHW6 tRDD6 tRDH6 Condition Min. 0 0 1000 450 500 10
ry a in
tCYCRD6
tRDH6
Typ.
Max.
250
Unit ns ns ns ns ns ns ns
Pin used CSB RS RDB(E)
D0~D15
VSS=0V , VDD = 2.4~2.7V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS RDB(E) D0~D15
350
VSS=0V , VDD = 1.8~2.4V , Ta = -30~+85 Item Address hold time Address setup time System cycle time in write Write pulse "L" width Write pulse "H" width Data setup time Data hold time Typ. Max. Unit ns ns ns ns ns ns ns Pin used CSB RS RDB(E) D0~D15
CL=80pF
650
Note: All the timings must be specified relative to 20% and 80% of VDD voltage. * This specification is subject to be changed without notice. 82 2003/1/9 (V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(5) Serial interface timing diagram
tCSS CSB tCSH
RS tASS tSLW SCL tDSS
tAHS
tSHW
tDHS
D0-D15
tCYCS
VSS=0V , VDD = 2.7~3.3V , Ta = -30~+85 Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH Condition Min. 200 80 80 40 40 80 80 40 40
VSS=0V , VDD = 2.4~2.7V , Ta = -30~+85 Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH
lim re P
Condition Min. 250 100 100 50 50 100 100 50 50 Symbol tCYCS tSHW tSLW tASS tAHS tDSS tDHS tCSS tCSH Condition Min. 1000 400 400 80 80 400 400 80 80
ry a in
Typ. Max. Unit ns ns ns ns ns ns ns ns ns Typ. Max. Unit ns ns ns ns ns ns ns ns ns
Pin used SCL RS
SDA CSB
Pin used SCL RS SDA CSB
VSS=0V , VDD = 1.8~2.4V , Ta = -30~+85 Item Serial clock period SCL pulse "H" width SCL pulse "L" width Address setup time Address hold time Data setup time Data hold time CSB-SCL time CSB hold time Typ. Max. Unit ns ns ns ns ns ns ns ns ns Pin used SCL RS SDA CSB
Note: All the timings must be specified relative to 20% and 80% of VDD voltage. * This specification is subject to be changed without notice. 83 2003/1/9 (V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(6) Display control timing
tCLKH tCLKL CLK tDLP tDLP tLPLW LP tLPHW tDFLM
tDFLM FLM tDM
M
Input timing (Slave mode) VSS=0V , VDD = 2.4~3.3V , Ta = -30~+85 Item CLK pulse "H" width CLK pulse "L" width LP pulse "H" width LP pulse "L" width LP delay time FLM delay time M delay time
Input timing (Slave mode) VSS=0V , VDD = 1.8~2.4V , Ta = -30~+85 Item CLK pulse "H" width CLK pulse "L" width LP pulse "H" width LP pulse "L" width LP delay time FLM delay time M delay time Symbol tCLKH tCLKL tLPHW tLPLW tDLP tDFLM tDM Condition Min. 1.6 1.6 80 80 -1 -1 -1 Typ. Max. Unit s s s s s s s Pin used CLK LP FLM M
lim re P
Condition CL =15 pF Min. 10 10 10
Symbol tCLKH tCLKL tLPHW tLPLW tDLP tDFLM tDM
Condition
Min. 1.6 1.6 80 80 -1 -1 -1
ry a in
Typ. Max. 1 1 1 Unit s s s s s s s 1 1 1
Pin used CLK LP FLM M
output timing (Master mode) VSS=0V , VDD = 2.4~3.3V , Ta = -30~+85 Item Symbol LP delay time tDLP FLM delay time tDFLM M delay time tDM Typ. Max. 500 500 500 Unit ns ns ns Pin used LP FLM M
output timing (Master mode) VSS=0V , VDD = 1.8~2.4V , Ta = -30~+85 Item Symbol LP delay time tDLP FLM delay time tDFLM M delay time tDM Condition CL =15 pF Min. 10 10 10 84 Typ. Max. 1000 1000 1000 Unit s s s Pin used LP FLM M 2003/1/9 (V0.1)
Note: All the timings must be specified relative to 20% and 80% of VDD voltage. * This specification is subject to be changed without notice.
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(7) Master clock input timing
tCKLW CK tCKHW
VSS=0V , VDD = 2.4~3.3V , Ta = -30~+85 Item CK pulse "H" width (1) CK pulse "L" width (1) CK pulse "H" width (2) CK pulse "L" width (2) CK pulse "H" width (3) CK pulse "L" width (3) Symbol tCKHW1 tCKLW1 tTCKHW2 tCKLW2 tCKHW3 tCKLW3 Condition Min. 1.2 1.2 5.4 5.4 38 38 Typ. Max. 1.4 1.4 6.5 6.5 45 45 Unit s s s s s s Pin used CK 1 CK 2 CK 3
VSS=0V , VDD = 1.8~2.4V , Ta = -30~+85 Item CK pulse "H" width (1) CK pulse "L" width (1) CK pulse "H" width (2) CK pulse "L" width (2) CK pulse "H" width (3) CK pulse "L" width (3) Symbol tCKHW1 tCKLW1 tCKHW2 tCKLW2 tCKHW3 tCKLW3
1 Applied when the gradation display mode. 2 Applied when the simple gradation mode. 3 Applied when the monochrome mode.
re P
in lim
Condition Note1 Note1 Note2 Note2 Note3 Note3 Min. 1.2 1.2 5.4 5.4 3.8 3.8 Typ.
ry a
Max. 1.4 1.4 6.5 6.5 4.5 4.5 Unit s s s s s s
Pin used CK 1 CK 2 CK 3
* This specification is subject to be changed without notice.
85
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(8) Reset timing
RESB
tRW tR
internal state
reset m ode
norm al dsiplay
VSS=0V, VDD = 2.4~3.3V, Ta = -30~+85 Item Reset time Reset pulse "L" width Symbol tR tRW Condition Min. 10 Typ. Max. 1 Unit s s Pin used RESB
VSS=0V, VDD = 1.8~2.4V, Ta = -30~+85 Item Reset time Reset pulse "L" width Symbol tR tRW Condition Min. 10
Note: All the timings must be specified relative to 20% and 80% of VDD voltage.
lim re P
ry a in
Typ. Max. 1.5 Unit s s
Pin used RESB
* This specification is subject to be changed without notice.
86
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
13.
Application circuit
(1) Connection to 80-family MCU
VCC A0 A1 to A7 80 fam ily MPU Decoder /IO RQ D0 to D7 /RD /W R /RES GND CSB RS
VDD
D0 to D7 RDB W RB RESB
EM65567 EM65567
(2) Connection to 68-family MCU
VCC A0 A1 to A15 68 fam ily MPU
lim re P
VSS VDD RS Decoder CSB D0 to D7 RDB(E) W RB(R/W ) RESB VSS
ry a in
VMA D0 to D7 E R/W /RES G ND
* This specification is subject to be changed without notice.
87
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(3) Connection to the MCU with serial interface
VCC A0 RS
VDD
A1 to A7 M PU
Decoder
CSB EM65567 VSS
PO RT1 PO RT2 /RES G ND
SDA SCL RESB
(4) Connection to Master / Slave about interface (parallel interface)
lim re P
EM65567(Master)
D0-D7 RESB WRB RDB M86 M/S R/S P/S
ry a in
EM65567 (Slave)
D0-D7 WRB RDB M86 M/S R/S P/S
RESB
CSB
CSB
VDD RESB CSB1 CSB2 RS WRB(R/W) RDB(E) D0-D7 M86
* This specification is subject to be changed without notice.
88
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
(5) Serial interface
EM65567 (Master) EM65567(Slave)
SCL SDA RDB WRB P/S M86 M/S R/S CSB RESB VDD RESB CSB1 CSB2 SDA SCL RS
SCL SDA RDB WRB P/S M86 M/S R/S CSB RESB
(6) Connection to master / slave about power block
VDD
lim re P
VEE VREF CAP1+ CAP1CAP2+ CAP2CAP3+ CAP3VOUT C1 VREG C3 C1 C1 C1 EM65567 (Master) V0 V1 C2 V0 V3 V1 V4 V2 CLK V3 LP V4 FLM M V2
VDD
ry a in
VDD VDD VEE VREF CAP1+ CAP1CAP2+ CAP2CAP3+ EM65567 (Slave) CAP3VOUT VREG V0 V1 V2 V3 V4 CLK LP FLM M
* This specification is subject to be changed without notice.
89
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
Caution of application about master / slave * The master chip control display timing (CLK,LP,FLM, and M). When making display OFF on the master chip, the master chip can not output the display timing. When making display OFF , beforehand set display OFF to the slave chip and set display OFF to the master chip. * When setting halt command, turn off the internal power supply, and output VSS level from LCD drive output pins , is set display OFF state. Because the master chip can not supply output voltage to the slave chip, beforehand set display OFF to the slave chip. *In above connection example, the master chip is only available the electronic volume control.
lim re P
ry a in
* This specification is subject to be changed without notice.
90
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
14. COF information
EM65567AF package Pin connection diagram (64 x 96RGB outputs)
lim re P
COM29 COM30 COM31 EM65567 : FACE DOW N
COM63 COM62 COM61 . . . . . . COM34 COM33 COM32 SEGC95 SEGB95 SEGA95 SEGC94 SEGB94 SEGA94 . . . . . . . . . SEGC1 SEGB1 SEGA1 SEGC0 SEGB0 SEGA0 COM0 COM1 COM2 . . . . . .
ry a in
VSS VDD V0 V1 V2 V3 V4 RESB CSB RS M/S P/S M86 W RB(R/W B) RDB(E) D0/SCL D1/SDA D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 LP FLM M CLK VSS CK CKS VDD VREF
* This specification is subject to be changed without notice.
91
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver


* This specification is subject to be changed without notice.
92
lim re P

ry a in
2003/1/9
(V0.1)
EM65567 66 COM/ 96 SEG 256 Color STN LCD Driver
lim re P
ry a in
* This specification is subject to be changed without notice.
93
2003/1/9
(V0.1)


▲Up To Search▲   

 
Price & Availability of EM65567AGH

All Rights Reserved © IC-ON-LINE 2003 - 2022  
[Add Bookmark] [Contact Us] [Link exchange] [Privacy policy]
Mirror Sites :  [www.datasheet.hk]   [www.maxim4u.com]  [www.ic-on-line.cn] [www.ic-on-line.com] [www.ic-on-line.net] [www.alldatasheet.com.cn] [www.gdcy.com]  [www.gdcy.net]
 . . . . .
  We use cookies to deliver the best possible web experience and assist with our advertising efforts. By continuing to use this site, you consent to the use of cookies. For more information on cookies, please take a look at our Privacy Policy. X